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authorLey Foon Tan <ley.foon.tan@intel.com>2020-06-10 13:24:16 +0800
committerMarek Vasut <marex@denx.de>2020-06-14 13:37:31 +0200
commita0bda1dd8382be57389833024ba40518ec098ac3 (patch)
treeb5a52818f4d7cee6c433dcec7d329310c740fb59 /arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
parentbe79009f3b9bbdbce283e67a865121e576d790ea (diff)
arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns
Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing calculation") change the hcnt and lcnt timing calculation. New timing calculation is based on calculation from Designware i2c databook. After this new timing calculation, hcnt will have negative value with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts. This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall time used in Designware i2c driver) for Uboot. Before the fix: => i2c dev 0 Setting bus to 0 Failure changing bus number (-22) After the fix: => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70 Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi')
-rw-r--r--arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
index 7d9874cafa..d24f621cd6 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
@@ -68,3 +68,7 @@
&portc {
bank-name = "portc";
};
+
+&i2c0 {
+ i2c-scl-falling-time-ns = <300>;
+};