diff options
| author | Marek Vasut <marex@denx.de> | 2018-05-07 22:22:26 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-07-25 00:13:32 +0200 |
| commit | 64eeb1585428b71e29022e22d1aae86b65b9e052 (patch) | |
| tree | e81ae5caa33279729457ea7ab0e93ff6c7ef5417 /arch/arm/dts/socfpga_arria10.dtsi | |
| parent | 42f4b83b52735d698bf3f3de2665bf6d42db9f1c (diff) | |
ARM: dts: socfpga: Adjust NAND register layout on Arria10
Adjust the NAND register size on Arria10 to reflect reality.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/dts/socfpga_arria10.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index b51febda9c..2f935a21e9 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -637,8 +637,8 @@ #address-cells = <1>; #size-cells = <1>; compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x72000>, - <0xffb80000 0x10000>; + reg = <0xffb90000 0x20>, + <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 99 4>; dma-mask = <0xffffffff>; |