diff options
author | Adam Ford <aford173@gmail.com> | 2021-12-06 10:29:28 -0600 |
---|---|---|
committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-12-13 00:37:28 +0100 |
commit | 61b3a0101acd5d1c08348fca85ac4c075be3f607 (patch) | |
tree | ba0de3271e90b0801774f151dfd3d02a3dd3d3f0 /arch/arm/dts/rz-g2-beacon-u-boot.dtsi | |
parent | 1eaf61c84db6100585fea4be20dbf8748c728685 (diff) |
arm: dts: Create common rz-g2-beacon-u-boot file
The rzg2_beacon_defconfig creates an image for RZ/G2[MNH] and
as such creates three different device trees and each of them
have a corresponding -u-boot.dtsi file which are basically
copies of each other. Create a common include file to be
referenced by each of the respective board-u-boot.dtsi files
to reduce duplicate code and simplify support going forward.
This also restores some lost functionality from the device
tree re-sync and updates the MAINTAINER file to include all
beacon-renesom device tree files.
Signed-off-by: Adam Ford <aford173@gmail.com>
Diffstat (limited to 'arch/arm/dts/rz-g2-beacon-u-boot.dtsi')
-rw-r--r-- | arch/arm/dts/rz-g2-beacon-u-boot.dtsi | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/arch/arm/dts/rz-g2-beacon-u-boot.dtsi b/arch/arm/dts/rz-g2-beacon-u-boot.dtsi new file mode 100644 index 00000000000..ef0b96a71ec --- /dev/null +++ b/arch/arm/dts/rz-g2-beacon-u-boot.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 LogicPD dba Beacon EmbeddedWorks + */ + +/ { + aliases { + spi0 = &rpc; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&cpg { + u-boot,dm-pre-reloc; +}; + +&ehci0 { + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>; +}; + +&ehci1 { + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>; +}; + +&extal_clk { + u-boot,dm-pre-reloc; +}; + +&extalr_clk { + u-boot,dm-pre-reloc; +}; + +&prr { + u-boot,dm-pre-reloc; +}; + +&rpc { + compatible = "renesas,rcar-gen3-rpc"; + num-cs = <1>; + spi-max-frequency = <40000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&sdhi0 { + /delete-property/ cd-gpios; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + status = "disabled"; +}; + +&sdhi3 { + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; +}; |