diff options
| author | Marty E. Plummer <hanetzer@startmail.com> | 2019-01-05 20:12:08 -0600 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2019-02-01 16:59:10 +0100 |
| commit | 8e2e601c5f5aff522cbdfff2445599d8d23827a0 (patch) | |
| tree | a24b47be3f81ea141cc181aa57225c7ddc91adc1 /arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | |
| parent | 09056c94a16c953aef029fb09832b6ea86a9a359 (diff) | |
rockchip: add support for veyron-speedy (ASUS Chromebook C201)
This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi')
| -rw-r--r-- | arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi new file mode 100644 index 0000000000..22ba3490f2 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2015 Google, Inc + */ + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; |