diff options
| author | Johan Jonker <jbx6244@gmail.com> | 2022-04-15 23:21:34 +0200 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2022-04-18 11:25:13 +0800 |
| commit | d886532a7c96345c0ccf90ce715b55f297be4256 (patch) | |
| tree | 21d8d62f7bfd49a4a2e3b74212d29bc665e32f4e /arch/arm/dts/rk322x.dtsi | |
| parent | 6914ef8e6773e490d4c6b412d21143b27bb00b02 (diff) | |
arm: dts: rockchip: move all rk322x u-boot specific properties in separate dtsi files
In order to sync rk322x.dtsi from Linux, move all
U-boot specific properties in separate dtsi files.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/dts/rk322x.dtsi')
| -rw-r--r-- | arch/arm/dts/rk322x.dtsi | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 4a8be5dabbd..3245da3c6af 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -107,22 +107,6 @@ #clock-cells = <0>; }; - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x9000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x9000>; - smp-sram@0 { - compatible = "rockchip,rk322x-smp-sram"; - reg = <0x00 0x10>; - }; - ddr_sram: ddr-sram@1000 { - compatible = "rockchip,rk322x-ddr-sram"; - reg = <0x1000 0x8000>; - }; - }; - i2s1: i2s1@100b0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100b0000 0x4000>; @@ -165,7 +149,6 @@ }; grf: syscon@11000000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3228-grf", "syscon"; reg = <0x11000000 0x1000>; }; @@ -317,7 +300,6 @@ }; cru: clock-controller@110e0000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3228-cru"; reg = <0x110e0000 0x1000>; rockchip,grf = <&grf>; @@ -387,7 +369,6 @@ sdmmc: dwmmc@30000000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30000000 0x4000>; - max-frequency = <150000000>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; @@ -414,7 +395,6 @@ emmc: dwmmc@30020000 { compatible = "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; - max-frequency = <150000000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; @@ -768,21 +748,4 @@ }; }; }; - - dmc: dmc@11200000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3228-dmc", "syscon"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,msch = <&service_msch>; - reg = <0x11200000 0x3fc - 0x12000000 0x400>; - rockchip,sram = <&ddr_sram>; - }; - - service_msch: syscon@31090000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3228-msch", "syscon"; - reg = <0x31090000 0x2000>; - }; }; |