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authorliu hao <steven_hao5189@outlook.com>2019-10-31 07:51:08 +0000
committerTom Rini <trini@konsulko.com>2019-11-07 18:01:13 -0500
commite3aafef4cf2d16e14e3bc02c3d8dbd434e305c19 (patch)
treefdbea6b74ff265944983e10293b5e401f4b61d77 /arch/arm/dts/phytium-durian.dts
parent672c57057f4071ee786c5a3b94897ff6b6de39c4 (diff)
arm: add initial support for the Phytium Durian Board
This adds platform code and the device tree for the Phytium Durian Board. The initial support comprises the UART and the PCIE. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
Diffstat (limited to 'arch/arm/dts/phytium-durian.dts')
-rw-r--r--arch/arm/dts/phytium-durian.dts33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/dts/phytium-durian.dts b/arch/arm/dts/phytium-durian.dts
new file mode 100644
index 0000000000..3b76949a26
--- /dev/null
+++ b/arch/arm/dts/phytium-durian.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Phytium Ltd.
+ * shuyiqi <shuyiqi@phytium.com.cn>
+ */
+
+/dts-v1/;
+
+/ {
+ model = "Phytium Durian";
+ compatible = "phytium,durian";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie-controller@40000000 {
+ compatible = "phytium,pcie-host-1.0";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0x0 0x40000000 0x0 0x10000000>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xF00000>,
+ <0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000>,
+ <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
+ };
+
+ uart@28001000 {
+ compatible = "arm,pl011";
+ reg = <0x0 0x28001000 0x0 0x1000>;
+ clock = <48000000>;
+ };
+};
+