diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2020-03-05 12:12:38 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2020-04-06 09:56:35 +0200 |
| commit | dd5f2351e99aad8fcbedbc1305b8b51b09952336 (patch) | |
| tree | 727bfd4c1de1adc8af73e5d0538876818cb9ea6f /arch/arm/dts/meson-gxm.dtsi | |
| parent | b3d69aa596599c7c940f7ad463c04b693589ff9a (diff) | |
arm64: dts: meson: sync dt and bindings from v5.6-rc2
Sync the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2")
The only exception to this is the mmc pinctrl pin bias of gxl SoC family.
This is a fix which found its way to u-boot but not Linux yet.
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'arch/arm/dts/meson-gxm.dtsi')
| -rw-r--r-- | arch/arm/dts/meson-gxm.dtsi | 39 |
1 files changed, 35 insertions, 4 deletions
diff --git a/arch/arm/dts/meson-gxm.dtsi b/arch/arm/dts/meson-gxm.dtsi index 247888d68a..5ff64a0d2d 100644 --- a/arch/arm/dts/meson-gxm.dtsi +++ b/arch/arm/dts/meson-gxm.dtsi @@ -44,7 +44,7 @@ cpu4: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2>; @@ -53,7 +53,7 @@ cpu5: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&l2>; @@ -62,7 +62,7 @@ cpu6: cpu@102 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&l2>; @@ -71,7 +71,7 @@ cpu7: cpu@103 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&l2>; @@ -91,6 +91,33 @@ reset-names = "phy"; status = "okay"; }; + + mali: gpu@c0000 { + compatible = "amlogic,meson-gxm-mali", "arm,mali-t820"; + reg = <0x0 0xc0000 0x0 0x40000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&clkc CLKID_MALI>; + resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc CLKID_MALI_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <666666666>, + <0>; /* Do Nothing */ + }; }; &clkc_AO { @@ -117,3 +144,7 @@ &dwc3 { phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; }; + +&vdec { + compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec"; +}; |