summaryrefslogtreecommitdiff
path: root/arch/arm/dts/kirkwood-98dx4122.dtsi
diff options
context:
space:
mode:
authorChris Packham <judge.packham@gmail.com>2018-05-08 22:34:10 +1200
committerStefan Roese <sr@denx.de>2018-05-17 17:35:25 +0200
commit060c85d41ca03b3002d26ba16f44beca99b63d64 (patch)
tree58471b4b4a77e307fa52f907e9fdb2432f979f93 /arch/arm/dts/kirkwood-98dx4122.dtsi
parentf2d0f5e7ab3b8a7b4bf6e2ac499b4867c701d52d (diff)
ARM: add devicetree files for kirkwood SoC
These files are taken verbatim from the Linux kernel 4.17 Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm/dts/kirkwood-98dx4122.dtsi')
-rw-r--r--arch/arm/dts/kirkwood-98dx4122.dtsi53
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/dts/kirkwood-98dx4122.dtsi b/arch/arm/dts/kirkwood-98dx4122.dtsi
new file mode 100644
index 00000000000..299c147298c
--- /dev/null
+++ b/arch/arm/dts/kirkwood-98dx4122.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+ mbus@f1000000 {
+ pciec: pcie@82000000 {
+ compatible = "marvell,kirkwood-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
+
+ pcie0: pcie@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &intc 9>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gate_clk 2>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ compatible = "marvell,98dx4122-pinctrl";
+
+ };
+ };
+};
+
+&sata_phy0 {
+ status = "disabled";
+};
+
+&sata_phy1 {
+ status = "disabled";
+};