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authorRavi Gunasekaran <r-gunasekaran@ti.com>2023-05-31 19:58:24 +0530
committerUdit Kumar <u-kumar1@ti.com>2023-05-31 20:23:34 +0530
commitaaf69b86dde2df62f7e4bd40ef22041366c2f178 (patch)
tree74223efd47ff3e756e6ab59766db2abff5b5fecc /arch/arm/dts/k3-j784s4-evm.dts
parent499ad65b510c0c2f3edf43e52e288abf71965214 (diff)
arm: dts: k3-j78s4: Enable SerDes for USB
Configure SerDes0 Lane 3 to USB and enable the SerDes related nodes Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org>
Diffstat (limited to 'arch/arm/dts/k3-j784s4-evm.dts')
-rw-r--r--arch/arm/dts/k3-j784s4-evm.dts31
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
index 7e0cf8e6ee..af0186c8ac 100644
--- a/arch/arm/dts/k3-j784s4-evm.dts
+++ b/arch/arm/dts/k3-j784s4-evm.dts
@@ -562,3 +562,34 @@
memory-region = <&c71_3_dma_memory_region>,
<&c71_3_memory_region>;
};
+
+&serdes_ln_ctrl {
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_usb_link: phy@3 {
+ reg = <3>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 4>;
+ };
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&usb_serdes_mux {
+ idle-states = <0>; /* USB0 to SERDES lane 3 */
+};