arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-Boot

Sync all J7200 related v5.11-rc6 Linux kernel dts into U-Boot.
MCU R5F nodes are not yet added in Linux kernel yet but were added
in U-Boot. In order to avoid regressions, r5f nodes are kept intact.
These will be added in kernel in future.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

1 files changed, 258 insertions, 38 deletions

diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index 9e6f738c64..1131464075 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -8,13 +8,34 @@
 &cbass_main {
 	msmc_ram: sram@70000000 {
 		compatible = "mmio-sram";
-		reg = <0x0 0x70000000 0x0 0x100000>;
+		reg = <0x00 0x70000000 0x00 0x100000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		ranges = <0x0 0x0 0x70000000 0x100000>;
+		ranges = <0x00 0x00 0x70000000 0x100000>;
 
 		atf-sram@0 {
-			reg = <0x0 0x20000>;
+			reg = <0x00 0x20000>;
+		};
+	};
+
+	scm_conf: scm-conf@100000 {
+		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+		reg = <0x00 0x00100000 0x00 0x1c000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+		serdes_ln_ctrl: serdes-ln-ctrl@4080 {
+			compatible = "mmio-mux";
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+					<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
+		};
+
+		usb_serdes_mux: mux-controller@4000 {
+			compatible = "mmio-mux";
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
 		};
 	};
 
@@ -40,11 +61,48 @@
 		};
 	};
 
-	main_navss: navss@30000000 {
+	main_gpio_intr: interrupt-controller0 {
+		compatible = "ti,sci-intr";
+		ti,intr-trigger-type = <1>;
+		interrupt-controller;
+		interrupt-parent = <&gic500>;
+		#interrupt-cells = <1>;
+		ti,sci = <&dmsc>;
+		ti,sci-dev-id = <131>;
+		ti,interrupt-ranges = <8 392 56>;
+	};
+
+	main_navss: bus@30000000 {
 		compatible = "simple-mfd";
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+		ti,sci-dev-id = <199>;
+
+		main_navss_intr: interrupt-controller1 {
+			compatible = "ti,sci-intr";
+			ti,intr-trigger-type = <4>;
+			interrupt-controller;
+			interrupt-parent = <&gic500>;
+			#interrupt-cells = <1>;
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <213>;
+			ti,interrupt-ranges = <0 64 64>,
+					      <64 448 64>,
+					      <128 672 64>;
+		};
+
+		main_udmass_inta: msi-controller@33d00000 {
+			compatible = "ti,sci-inta";
+			reg = <0x00 0x33d00000 0x00 0x100000>;
+			interrupt-controller;
+			#interrupt-cells = <0>;
+			interrupt-parent = <&main_navss_intr>;
+			msi-controller;
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <209>;
+			ti,interrupt-ranges = <0 0 256>;
+		};
 
 		secure_proxy_main: mailbox@32c00000 {
 			compatible = "ti,am654-secure-proxy";
@@ -56,12 +114,174 @@
 			interrupt-names = "rx_011";
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		hwspinlock: spinlock@30e00000 {
+			compatible = "ti,am654-hwspinlock";
+			reg = <0x00 0x30e00000 0x00 0x1000>;
+			#hwlock-cells = <1>;
+		};
+
+		mailbox0_cluster0: mailbox@31f80000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f80000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster1: mailbox@31f81000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f81000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster2: mailbox@31f82000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f82000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster3: mailbox@31f83000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f83000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster4: mailbox@31f84000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f84000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster5: mailbox@31f85000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f85000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster6: mailbox@31f86000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f86000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster7: mailbox@31f87000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f87000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster8: mailbox@31f88000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f88000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster9: mailbox@31f89000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f89000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster10: mailbox@31f8a000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8a000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		mailbox0_cluster11: mailbox@31f8b000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8b000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			interrupt-parent = <&main_navss_intr>;
+		};
+
+		main_ringacc: ringacc@3c000000 {
+			compatible = "ti,am654-navss-ringacc";
+			reg =	<0x00 0x3c000000 0x00 0x400000>,
+				<0x00 0x38000000 0x00 0x400000>,
+				<0x00 0x31120000 0x00 0x100>,
+				<0x00 0x33000000 0x00 0x40000>;
+			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+			ti,num-rings = <1024>;
+			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <211>;
+			msi-parent = <&main_udmass_inta>;
+		};
+
+		main_udmap: dma-controller@31150000 {
+			compatible = "ti,j721e-navss-main-udmap";
+			reg =	<0x00 0x31150000 0x00 0x100>,
+				<0x00 0x34000000 0x00 0x100000>,
+				<0x00 0x35000000 0x00 0x100000>;
+			reg-names = "gcfg", "rchanrt", "tchanrt";
+			msi-parent = <&main_udmass_inta>;
+			#dma-cells = <1>;
+
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <212>;
+			ti,ringacc = <&main_ringacc>;
+
+			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+						<0x0f>, /* TX_HCHAN */
+						<0x10>; /* TX_UHCHAN */
+			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+						<0x0b>, /* RX_HCHAN */
+						<0x0c>; /* RX_UHCHAN */
+			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+		};
+
+		cpts@310d0000 {
+			compatible = "ti,j721e-cpts";
+			reg = <0x00 0x310d0000 0x00 0x400>;
+			reg-names = "cpts";
+			clocks = <&k3_clks 201 1>;
+			clock-names = "cpts";
+			interrupts-extended = <&main_navss_intr 391>;
+			interrupt-names = "cpts";
+			ti,cpts-periodic-outputs = <6>;
+			ti,cpts-ext-ts-inputs = <8>;
+		};
 	};
 
-	main_pmx0: pinmux@11c000 {
+	main_pmx0: pinctrl@11c000 {
 		compatible = "pinctrl-single";
 		/* Proxy 0 addressing */
-		reg = <0x0 0x11c000 0x0 0x2b4>;
+		reg = <0x00 0x11c000 0x00 0x2b4>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
 		pinctrl-single,function-mask = <0xffffffff>;
@@ -197,28 +417,6 @@
 		clock-names = "fclk";
 	};
 
-	main_gpio0: gpio@600000 {
-		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
-		reg = <0x0 0x00600000 0x0 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
-			     <105 1 IRQ_TYPE_EDGE_RISING>,
-			     <105 2 IRQ_TYPE_EDGE_RISING>,
-			     <105 3 IRQ_TYPE_EDGE_RISING>,
-			     <105 4 IRQ_TYPE_EDGE_RISING>,
-			     <105 5 IRQ_TYPE_EDGE_RISING>,
-			     <105 6 IRQ_TYPE_EDGE_RISING>,
-			     <105 7 IRQ_TYPE_EDGE_RISING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <69>;
-		ti,davinci-gpio-unbanked = <0>;
-		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 105 0>;
-		clock-names = "gpio";
-	};
-
 	main_sdhci0: sdhci@4f80000 {
 		compatible = "ti,j721e-sdhci-8bit";
 		reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
@@ -259,18 +457,18 @@
 
 	main_i2c0: i2c@2000000 {
 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2000000 0x0 0x100>;
+		reg = <0x00 0x2000000 0x00 0x100>;
 		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		clock-names = "fck";
 		clocks = <&k3_clks 187 1>;
-		power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+		power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
 	};
 
 	main_i2c1: i2c@2010000 {
 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2010000 0x0 0x100>;
+		reg = <0x00 0x2010000 0x00 0x100>;
 		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -281,7 +479,7 @@
 
 	main_i2c2: i2c@2020000 {
 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2020000 0x0 0x100>;
+		reg = <0x00 0x2020000 0x00 0x100>;
 		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -292,7 +490,7 @@
 
 	main_i2c3: i2c@2030000 {
 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2030000 0x0 0x100>;
+		reg = <0x00 0x2030000 0x00 0x100>;
 		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -303,7 +501,7 @@
 
 	main_i2c4: i2c@2040000 {
 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2040000 0x0 0x100>;
+		reg = <0x00 0x2040000 0x00 0x100>;
 		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -314,7 +512,7 @@
 
 	main_i2c5: i2c@2050000 {
 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2050000 0x0 0x100>;
+		reg = <0x00 0x2050000 0x00 0x100>;
 		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -325,7 +523,7 @@
 
 	main_i2c6: i2c@2060000 {
 		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x2060000 0x0 0x100>;
+		reg = <0x00 0x2060000 0x00 0x100>;
 		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -334,13 +532,35 @@
 		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
 	};
 
-	usbss0: cdns_usb@4104000 {
+	main_gpio0: gpio@600000 {
+		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+		reg = <0x0 0x00600000 0x0 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
+			     <105 1 IRQ_TYPE_EDGE_RISING>,
+			     <105 2 IRQ_TYPE_EDGE_RISING>,
+			     <105 3 IRQ_TYPE_EDGE_RISING>,
+			     <105 4 IRQ_TYPE_EDGE_RISING>,
+			     <105 5 IRQ_TYPE_EDGE_RISING>,
+			     <105 6 IRQ_TYPE_EDGE_RISING>,
+			     <105 7 IRQ_TYPE_EDGE_RISING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		ti,ngpio = <69>;
+		ti,davinci-gpio-unbanked = <0>;
+		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 105 0>;
+		clock-names = "gpio";
+	};
+
+	usbss0: cdns-usb@4104000 {
 		compatible = "ti,j721e-usb";
 		reg = <0x00 0x4104000 0x00 0x100>;
 		dma-coherent;
 		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
-		clock-names = "usb2_refclk", "lpm_clk";
+		clock-names = "ref", "lpm";
 		assigned-clocks = <&k3_clks 288 12>;	/* USB2_REFCLK */
 		assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
 		#address-cells = <2>;