diff options
author | Bryan Brattlof <bb@ti.com> | 2023-10-23 16:35:24 -0500 |
---|---|---|
committer | Praneeth Bajjuri <praneeth@ti.com> | 2023-10-24 15:35:42 -0500 |
commit | 5014368187db197fbe1a629528c26e659e94cfe5 (patch) | |
tree | 757dfeafae548a8e79d7bf870ec77029dad6faba /arch/arm/dts/k3-am62p5.dtsi | |
parent | 9fa86d1770a63fd41c881f7b8db51daf5104ea75 (diff) |
arm: dts: add am62p5 dtbs from linux
Pull in the device tree source files for TI's am62p5 SoCs needed to boot
the board from v6.6-rc5. These are an early release with only the
peripherals to boot the board via UART boot
[bb@ti.com: used DTBs from TI's v6.1 kernel]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Diffstat (limited to 'arch/arm/dts/k3-am62p5.dtsi')
-rw-r--r-- | arch/arm/dts/k3-am62p5.dtsi | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-am62p5.dtsi b/arch/arm/dts/k3-am62p5.dtsi new file mode 100644 index 0000000000..50147bb63e --- /dev/null +++ b/arch/arm/dts/k3-am62p5.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5 SoC family (quad core) + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * TRM: https://www.ti.com/lit/pdf/spruj83 + */ + +/dts-v1/; + +#include "k3-am62p.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; |