diff options
| author | Ye Li <ye.li@nxp.com> | 2022-01-10 16:21:28 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-04-18 14:03:40 +0800 |
| commit | 8caf88e72cfff5092ea4fdf7814200d72123126c (patch) | |
| tree | aedd5c747d6dc45d33ae6057b425952e1c5119b9 /arch/arm/dts/imx8ulp-9x9-evk.dts | |
| parent | bd20464ed1e92da7892ba4109a445aba6f669ccf (diff) | |
LFU-277 imx8ulp_evk: Add iMX8ULP 9x9 EVK support
Add below changes to support 9x9 EVK board:
1. Add a dedicated DTS for 9x9 EVK, change the pinmux for DSI reset,
ENET, USB1/2 ID and OC.
2. Update DDR timing file for DQ mapping changed
3. Change kernel DTB to imx8ulp-9x9-evk.dtb
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit b887b38a9212a16643c1f506bfa6e2dd80621045)
(cherry picked from commit 8752ce826280c03e1d4926dfff54f7d81977cdc3)
Diffstat (limited to 'arch/arm/dts/imx8ulp-9x9-evk.dts')
| -rw-r--r-- | arch/arm/dts/imx8ulp-9x9-evk.dts | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8ulp-9x9-evk.dts b/arch/arm/dts/imx8ulp-9x9-evk.dts new file mode 100644 index 0000000000..81adc5d69c --- /dev/null +++ b/arch/arm/dts/imx8ulp-9x9-evk.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 NXP + */ + +/dts-v1/; + +#include "imx8ulp-evk.dts" +#include "imx8ulp-evk-u-boot.dtsi" + +/ { + model = "NXP i.MX8ULP 9X9 EVK"; +}; + +&{/soc@0/bus@2d800000/dsi@2db00000/panel@0} { + reset-gpios = <&gpiof 21 GPIO_ACTIVE_LOW>; +}; + +&pinctrl_dsi { + fsl,pins = < + MX8ULP_PAD_PTF21__PTF21 0x3 + >; +}; + +&pinctrl_enet { + fsl,pins = < + MX8ULP_PAD_PTF9__ENET0_MDC 0x43 + MX8ULP_PAD_PTF8__ENET0_MDIO 0x43 + MX8ULP_PAD_PTF5__ENET0_RXER 0x43 + MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43 + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 + MX8ULP_PAD_PTF0__ENET0_RXD1 0x43 + MX8ULP_PAD_PTF4__ENET0_TXEN 0x43 + MX8ULP_PAD_PTF3__ENET0_TXD0 0x43 + MX8ULP_PAD_PTF2__ENET0_TXD1 0x43 + MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43 + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 + >; +}; + +&pinctrl_otgid1 { + fsl,pins = < + MX8ULP_PAD_PTE16__USB0_ID 0x10003 + MX8ULP_PAD_PTE18__USB0_OC 0x10003 + >; +}; + +&pinctrl_otgid2 { + fsl,pins = < + MX8ULP_PAD_PTD23__USB1_ID 0x10003 + MX8ULP_PAD_PTE20__USB1_OC 0x10003 + >; +};
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