diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2022-07-21 15:27:26 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-07-25 16:12:00 +0200 |
| commit | d0399a46e7cda63c07e3eb8558bef84cfb068028 (patch) | |
| tree | 109f7d723e2c5fecc52355e6fcb39b7107c12b16 /arch/arm/dts/imx6qdl-sr-som.dtsi | |
| parent | 50b229523bbc5511e1bace34df779f84950bf872 (diff) | |
imx6dl/imx6qdl: synchronise device trees with linux
Synchronise device trees with linux-next next-20220708.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm/dts/imx6qdl-sr-som.dtsi')
| -rw-r--r-- | arch/arm/dts/imx6qdl-sr-som.dtsi | 31 |
1 files changed, 22 insertions, 9 deletions
diff --git a/arch/arm/dts/imx6qdl-sr-som.dtsi b/arch/arm/dts/imx6qdl-sr-som.dtsi index c20bed2721..ce543e325c 100644 --- a/arch/arm/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/dts/imx6qdl-sr-som.dtsi @@ -53,7 +53,6 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; - phy-handle = <&phy>; phy-mode = "rgmii-id"; /* @@ -69,16 +68,30 @@ #address-cells = <1>; #size-cells = <0>; - phy: ethernet-phy@0 { - /* - * The PHY can appear either: - * - AR8035: at address 0 or 4 - * - ADIN1300: at address 1 - * Actual address being detected at runtime. - */ - reg = <0xffffffff>; + /* + * The PHY can appear at either address 0 or 4 due to the + * configuration (LED) pin not being pulled sufficiently. + */ + ethernet-phy@0 { + reg = <0>; qca,clk-out-frequency = <125000000>; + qca,smarteee-tw-us-1g = <24>; + }; + + ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + qca,smarteee-tw-us-1g = <24>; + }; + + /* + * ADIN1300 (som rev 1.9 or later) is always at address 1. It + * will be enabled automatically by U-Boot if detected. + */ + ethernet-phy@1 { + reg = <1>; adi,phy-output-clock = "125mhz-free-running"; + status = "disabled"; }; }; }; |