diff options
| author | Gaurav Jain <gaurav.jain@nxp.com> | 2022-03-24 11:50:32 +0530 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-04-06 13:46:54 +0800 |
| commit | 61c3ad1c7fdaaa006a4950cc0e7e17eeb3cbaaf7 (patch) | |
| tree | c0a4a30510c3d3350f1a71013e8f8119c5105366 /arch/arm/dts/fsl-imx8qm.dtsi | |
| parent | 79ad7fa5beb9f5e25c3004ad37c9daa7d471504f (diff) | |
i.MX8: Add crypto node in device tree
i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.
disabled use of JR1 in SPL and uboot, as JR1 is reserved
for SECO FW.
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch/arm/dts/fsl-imx8qm.dtsi')
| -rw-r--r-- | arch/arm/dts/fsl-imx8qm.dtsi | 61 |
1 files changed, 60 insertions, 1 deletions
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi index 88aeaf65b3..517fb13cad 100644 --- a/arch/arm/dts/fsl-imx8qm.dtsi +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -235,6 +235,30 @@ wakeup-irq = <349>; }; }; + + pd_caam: PD_CAAM { + compatible = "nxp,imx8-pd"; + reg = <SC_R_NONE>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_caam_jr1: PD_CAAM_JR1 { + reg = <SC_R_CAAM_JR1>; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr2: PD_CAAM_JR2 { + reg = <SC_R_CAAM_JR2>; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr3: PD_CAAM_JR3 { + reg = <SC_R_CAAM_JR3>; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + }; }; i2c0: i2c@5a800000 { @@ -556,6 +580,41 @@ power-domains = <&pd_conn_enet1>; status = "disabled"; }; + + crypto: caam@0x31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0 0x31400000 0 0x400000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x31400000 0x400000>; + fsl,first-jr-index = <2>; + fsl,sec-era = <9>; + + sec_jr1: jr1@0x20000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x1000>; + interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_caam_jr1>; + status = "disabled"; + }; + + sec_jr2: jr2@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x1000>; + interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_caam_jr2>; + status = "okay"; + }; + + sec_jr3: jr3@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x1000>; + interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_caam_jr3>; + status = "okay"; + }; + }; }; &A53_0 { |