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authorLeonid Lobachev <leonidl@google.com>2018-06-04 18:49:19 -0700
committerJi Luo <ji.luo@nxp.com>2019-04-11 14:01:28 +0800
commit646103f3df9ad99be9f74058d2c7cf4334d58bf3 (patch)
treefbff43d429fbd49a5befbbcabd1a099826850c91 /arch/arm/dts/fsl-imx8mq-aiy.dts
parent639e5c15816c3eea0d4904a72ad175627be043d8 (diff)
MA-14518 AIY: Enable i2c2 and i2c3 in u-boot.
Enable i2c2 and i2c3 for AIY. Change-Id: I984e2e76e7c8929cc62088b6838c81f5dc838568
Diffstat (limited to 'arch/arm/dts/fsl-imx8mq-aiy.dts')
-rw-r--r--arch/arm/dts/fsl-imx8mq-aiy.dts17
1 files changed, 15 insertions, 2 deletions
diff --git a/arch/arm/dts/fsl-imx8mq-aiy.dts b/arch/arm/dts/fsl-imx8mq-aiy.dts
index 43165545e5..7453e302c7 100644
--- a/arch/arm/dts/fsl-imx8mq-aiy.dts
+++ b/arch/arm/dts/fsl-imx8mq-aiy.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2018 NXP
+ * Copyright 2019 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -187,6 +187,12 @@
>;
};
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
+ >;
+ };
pinctrl_pcie0: pcie0grp {
fsl,pins = <
@@ -568,7 +574,14 @@
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
- status = "disabled";
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
};
&pcie0{