MLK-22759-3 imx8mn: Add LPDDR4 EVK board support

Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and
PCA9450B PMIC.

Signed-off-by: Ye Li <ye.li@nxp.com>

1 files changed, 497 insertions, 0 deletions

diff --git a/arch/arm/dts/fsl-imx8mn-evk.dts b/arch/arm/dts/fsl-imx8mn-evk.dts
new file mode 100644
index 00000000000..5d5943421f6
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mn-evk.dts
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8mn.dtsi"
+
+/ {
+	model = "NXP i.MX8MNano LPDDR4 EVK board";
+	compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
+
+	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+		stdout-path = &uart2;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		startup-delay-us = <100>;
+		off-on-delay-us = <12000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx8mn-evk {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX8MN_IOMUXC_GPIO1_IO08__GPIO1_IO8		0x16
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MN_IOMUXC_ENET_MDC__ENET1_MDC		0x3
+				MX8MN_IOMUXC_ENET_MDIO__ENET1_MDIO	0x3
+				MX8MN_IOMUXC_ENET_TD3__ENET1_RGMII_TD3	0x1f
+				MX8MN_IOMUXC_ENET_TD2__ENET1_RGMII_TD2	0x1f
+				MX8MN_IOMUXC_ENET_TD1__ENET1_RGMII_TD1	0x1f
+				MX8MN_IOMUXC_ENET_TD0__ENET1_RGMII_TD0	0x1f
+				MX8MN_IOMUXC_ENET_RD3__ENET1_RGMII_RD3	0x91
+				MX8MN_IOMUXC_ENET_RD2__ENET1_RGMII_RD2	0x91
+				MX8MN_IOMUXC_ENET_RD1__ENET1_RGMII_RD1	0x91
+				MX8MN_IOMUXC_ENET_RD0__ENET1_RGMII_RD0	0x91
+				MX8MN_IOMUXC_ENET_TXC__ENET1_RGMII_TXC	0x1f
+				MX8MN_IOMUXC_ENET_RXC__ENET1_RGMII_RXC	0x91
+				MX8MN_IOMUXC_ENET_RX_CTL__ENET1_RGMII_RX_CTL	0x91
+				MX8MN_IOMUXC_ENET_TX_CTL__ENET1_RGMII_TX_CTL	0x1f
+				MX8MN_IOMUXC_SAI2_RXC__GPIO4_IO22	0x19
+			>;
+		};
+
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				MX8MN_IOMUXC_NAND_ALE__QSPI_A_SCLK 0x1c4
+				MX8MN_IOMUXC_NAND_CE0_B__QSPI_A_SS0_B 0x84
+
+				MX8MN_IOMUXC_NAND_DQS__QSPI_A_DQS 0x40000084
+				MX8MN_IOMUXC_NAND_DATA00__QSPI_A_DATA0 0x84
+				MX8MN_IOMUXC_NAND_DATA01__QSPI_A_DATA1 0x84
+				MX8MN_IOMUXC_NAND_DATA02__QSPI_A_DATA2 0x84
+				MX8MN_IOMUXC_NAND_DATA03__QSPI_A_DATA3 0x84
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MN_IOMUXC_I2C1_SCL__I2C1_SCL			0x400001c3
+				MX8MN_IOMUXC_I2C1_SDA__I2C1_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MN_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
+				MX8MN_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX8MN_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
+				MX8MN_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp-gpio {
+			fsl,pins = <
+				MX8MN_IOMUXC_I2C1_SCL__GPIO5_IO14        		0x1c3
+				MX8MN_IOMUXC_I2C1_SDA__GPIO5_IO15        	0x1c3
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grp-gpio {
+			fsl,pins = <
+				MX8MN_IOMUXC_I2C2_SCL__GPIO5_IO16        		0x1c3
+				MX8MN_IOMUXC_I2C2_SDA__GPIO5_IO17        	0x1c3
+			>;
+		};
+
+		pinctrl_i2c3_gpio: i2c3grp-gpio {
+			fsl,pins = <
+				MX8MN_IOMUXC_I2C3_SCL__GPIO5_IO18        		0x1c3
+				MX8MN_IOMUXC_I2C3_SDA__GPIO5_IO19        	0x1c3
+			>;
+		};
+
+		pinctrl_pmic: pmicirq {
+			fsl,pins = <
+				MX8MN_IOMUXC_GPIO1_IO03__GPIO1_IO3		0x41
+			>;
+		};
+
+		pinctrl_uart2: uart1grp {
+			fsl,pins = <
+				MX8MN_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
+				MX8MN_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MN_IOMUXC_GPIO1_IO15__GPIO1_IO15	0x1c4
+				MX8MN_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
+				MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
+				MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
+				MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
+				MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
+				MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
+				MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
+				MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
+				MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
+				MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
+				MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
+				MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
+				MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
+				MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
+				MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
+				MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
+				MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
+				MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
+				MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK		0x40000190
+				MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
+				MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
+				MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
+				MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
+				MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
+				MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
+				MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
+				MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
+				MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
+				MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 		0x190
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK		0x40000194
+				MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
+				MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
+				MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
+				MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
+				MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
+				MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
+				MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
+				MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
+				MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
+				MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 		0x194
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK		0x40000196
+				MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
+				MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
+				MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
+				MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
+				MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
+				MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
+				MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
+				MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
+				MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
+				MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE 		0x196
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MN_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
+			>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pca9450@25 {
+		reg = <0x25>;
+		compatible = "nxp,pca9450b";
+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+		pinctrl-0 = <&pinctrl_pmic>;
+		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+		gpo {
+			nxp,drv = <0x0C>;	/* 0b0000_1100 all gpos with cmos output mode */
+		};
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9450,pmic-buck2-uses-i2c-dvs;
+			pca9450,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
+				regulator-compatible = "buck1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2_reg: regulator@1 {
+				reg = <1>;
+				regulator-compatible = "buck2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck3_reg: regulator@2 {
+				reg = <2>;
+				regulator-compatible = "buck3";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: regulator@3 {
+				reg = <3>;
+				regulator-compatible = "buck4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: regulator@4 {
+				reg = <4>;
+				regulator-compatible = "buck5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: regulator@5 {
+				reg = <5>;
+				regulator-compatible = "buck6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: regulator@6 {
+				reg = <6>;
+				regulator-compatible = "ldo1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: regulator@7 {
+				reg = <7>;
+				regulator-compatible = "ldo2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: regulator@8 {
+				reg = <8>;
+				regulator-compatible = "ldo3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: regulator@9 {
+				reg = <9>;
+				regulator-compatible = "ldo4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: regulator@10 {
+				reg = <10>;
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	typec_ptn5110_1: ptn5110@50 {
+		compatible = "usb,tcpci";
+		reg = <0x50>;
+		src-pdos = <0x380190c8>;
+		snk-pdos = <0x380190c8 0x3802d0c8>;
+		max-snk-mv = <9000>;
+		max-snk-ma = <2000>;
+		op-snk-mw = <9000>;
+		max-snk-mw = <18000>;
+		port-type = "drp";
+		default-role = "sink";
+	};
+
+	typec_ptn5110_2: ptn5110@52 {
+		compatible = "usb,tcpci";
+		reg = <0x52>;
+		src-pdos = <0x380190c8>;
+		snk-pdos = <0x380190c8 0x3802d0c8>;
+		max-snk-mv = <9000>;
+		max-snk-ma = <2000>;
+		op-snk-mw = <9000>;
+		max-snk-mw = <18000>;
+		port-type = "drp";
+		default-role = "sink";
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: n25q256a@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-okay;
+			at803x,vddio-1p8v;
+		};
+	};
+};
+
+&uart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&A53_0 {
+	arm-supply = <&buck2_reg>;
+};
+
+&usbotg1 {
+	status = "okay";
+	extcon = <&typec_ptn5110_1>;
+};
+
+&usbotg2 {
+	status = "okay";
+	extcon = <&typec_ptn5110_2>;
+};