diff options
| author | Ye Li <ye.li@nxp.com> | 2020-11-02 22:06:53 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-04-06 18:04:13 +0800 |
| commit | f5a58577c427125a619a0940593510081cbf2564 (patch) | |
| tree | 875bbbbecf8404bd58db550845d28a52f37d3b82 /arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts | |
| parent | d9303e79126526507441f59d8eafc90f70e56e85 (diff) | |
MLK-24958-4 DTS: imx8dxl-evk: Add dedicated DTS for LCD enablemennt
Because LCDIF has lots of pinmux conflict with modules like eQOS, SPI,
ADC, LPUART1, etc. We can't support it by default.
Introduce a new DTS for LCDIF enablement and disable conflicted nodes.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 39840421d4e2d805df1420658629e78925f41490)
(cherry picked from commit 6a402cfcea13b6d34f9c9adb036ecc1bcf161139)
(cherry picked from commit 2d8a314fea42ed5985e2e976af0a7c8c644362f2)
(cherry picked from commit 99460f617b13a4eb1aab04cf00c1813fc6cc4d11)
Diffstat (limited to 'arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts')
| -rw-r--r-- | arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts b/arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts new file mode 100644 index 0000000000..8ff96eeec0 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "fsl-imx8dxl-evk.dts" +#include "fsl-imx8dxl-evk-u-boot.dtsi" + +&eqos { + status = "disabled"; +}; + +&lpspi3 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + SC_P_SPI3_SCK_ADMA_LCDIF_D00 0x00000023 + SC_P_SPI3_SDO_ADMA_LCDIF_D01 0x00000023 + SC_P_SPI3_SDI_ADMA_LCDIF_D02 0x00000023 + SC_P_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 0x00000023 + SC_P_UART1_TX_ADMA_LCDIF_D04 0x00000023 + SC_P_UART1_RX_ADMA_LCDIF_D05 0x00000023 + SC_P_UART1_RTS_B_ADMA_LCDIF_D06 0x00000023 + SC_P_UART1_CTS_B_ADMA_LCDIF_D07 0x00000023 + SC_P_SPI0_SCK_ADMA_LCDIF_D08 0x00000023 + SC_P_SPI0_SDI_ADMA_LCDIF_D09 0x00000023 + SC_P_SPI0_SDO_ADMA_LCDIF_D10 0x00000023 + SC_P_SPI0_CS1_ADMA_LCDIF_D11 0x00000023 + SC_P_SPI0_CS0_ADMA_LCDIF_D12 0x00000023 + SC_P_ADC_IN1_ADMA_LCDIF_D13 0x00200003 + SC_P_ADC_IN0_ADMA_LCDIF_D14 0x00200003 + SC_P_ADC_IN3_ADMA_LCDIF_D15 0x00200003 + SC_P_ADC_IN2_ADMA_LCDIF_D16 0x00200003 + SC_P_ADC_IN5_ADMA_LCDIF_D17 0x00200003 + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000023 + SC_P_SPI3_CS1_ADMA_LCDIF_RESET 0x00000023 + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000023 + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000023 + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000023 + >; + }; +}; + +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + assigned-clocks = <&clk IMX8QXP_LCD_SEL>, + <&clk IMX8QXP_LCD_PXL_SEL>, + <&clk IMX8QXP_ELCDIF_PLL_DIV>; + assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>, + <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; + assigned-clock-rates = <0>, <0>, <711000000>; + + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <18>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <71100000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <70>; + hback-porch = <80>; + hsync-len = <10>; + vback-porch = <10>; + vfront-porch = <10>; + vsync-len = <3>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; |