diff options
author | Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> | 2018-01-10 11:33:50 +0100 |
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committer | Tom Rini <trini@konsulko.com> | 2018-01-15 16:29:02 -0500 |
commit | 4b684a6b82572654b7398d871aa138398c2b18c7 (patch) | |
tree | 66aaaaa9f44d7d26f6509caca78fe35d1f4c68e7 /arch/arm/dts/dragonboard820c.dts | |
parent | 7c75f7f1b29eb53912b75472f4d8135c465f87f5 (diff) |
db820c: add qualcomm dragonboard 820C support
This commit adds support for 96Boards Dragonboard820C.
The board is based on APQ8086 Qualcomm Soc, complying with the
96Boards specification.
Features
- 4x Kyro CPU (64 bit) up to 2.15GHz
- USB2.0
- USB3.0
- ISP
- Qualcomm Hexagon DSP
- SD 3.0 (UHS-I)
- UFS 2.0
- Qualcomm Adreno 530 GPU
- GPS
- BT 4.2
- Wi-Fi 2.4GHz, 5GHz (802.11ac)
- PCIe 2.0
- MIPI-CSI, MIPI-DSI
- I2S
U-Boot boots chained from LK (LK implements the fastboot protocol) in
64-bit mode.
For detailed build instructions see readme.txt in the board directory.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Diffstat (limited to 'arch/arm/dts/dragonboard820c.dts')
-rw-r--r-- | arch/arm/dts/dragonboard820c.dts | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts new file mode 100644 index 00000000000..2d49830e772 --- /dev/null +++ b/arch/arm/dts/dragonboard820c.dts @@ -0,0 +1,65 @@ +/* + * Qualcomm APQ8096 based Dragonboard 820C board device tree source + * + * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton64.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DB820c"; + compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &blsp2_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0xc0000000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@300000 { + compatible = "qcom,gcc-msm8996"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x300000 0x90000>; + }; + + blsp2_uart1: serial@75b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x75b0000 0x1000>; + }; + + sdhc2: sdhci@74a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x74a4900 0x314>, <0x74a4000 0x800>; + index = <0x0>; + bus-width = <4>; + clock = <&gcc 0>; + clock-frequency = <200000000>; + }; + }; +}; |