diff options
| author | Robert Marko <robert.marko@sartura.hr> | 2021-10-04 15:12:53 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2021-10-08 08:37:55 +0200 |
| commit | cfb7102d8d901e9bdc7a6c109b341de7ae84256d (patch) | |
| tree | d11a383a303dfbb161dd180341ac8a1e18e630c3 /arch/arm/dts/armada-8040-puzzle-m801.dts | |
| parent | cf47a8cf8f7e53018bff9952183b7cbf45b07c30 (diff) | |
arm: mvebu: dts: m801: correct CP1 pinctrl
Current CP1 pinctrl that is set on the Puzzle M801 is incorrect.
CP1 pins are only used for the SMI bus and the MSS I2C, all other
pins are just GPIO-s.
Due to this being set completely wrong, the pinctrl was actually
ended up being hardcoded in the board_early_init_f() step so that
SMI would work.
That is obviously not the right thing to do, so convert the register
hex values that were being written to individual pin modes and set it
in the DTS.
Add the SMI pins to the CP1 MDIO node as otherwise CP1 pinctrl does
not get probed without an consumer.
Fixes: 2ae2b8a2 ("arm: mvebu: Initial iEi Puzzle-M801 support")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm/dts/armada-8040-puzzle-m801.dts')
| -rw-r--r-- | arch/arm/dts/armada-8040-puzzle-m801.dts | 36 |
1 files changed, 15 insertions, 21 deletions
diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index 510fb84d5a..9e714c33e9 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -243,6 +243,9 @@ &cp1_mdio { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_smi_pins>; + cp1_ge_phy0: ethernet-phy@3 { reg = <1>; }; @@ -292,33 +295,24 @@ /* * MPP Bus: * [0-5] TDM - * [6,7] CP1_UART 0 - * [8] CP1 10G SFP LOS - * [9] CP1 10G PHY RESET - * [10] CP1 10G SFP TX Disable - * [11] CP1 10G SFP Mode - * [12] SPI1 CS1n - * [13] SPI1 MISO (TDM and SPI ROM shared) - * [14] SPI1 CS0n - * [15] SPI1 MOSI (TDM and SPI ROM shared) - * [16] SPI1 CLK (TDM and SPI ROM shared) - * [24] CP1 2.5G SFP TX Disable - * [26] CP0 10G SFP TX Fault - * [27] CP0 10G SFP Mode - * [28] CP0 10G SFP LOS - * [29] CP0 10G SFP TX Disable - * [30] USB Over current indication - * [31] 10G Port 0 phy reset + * [27-28] SMI + * [29-30] CP1 MSS I2C + * [6-26, 31] GPIO * [32-62] = 0xff: Keep default CP1_shared_pins: */ /* 0 1 2 3 4 5 6 7 8 9 */ - pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0 - 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff - 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0 - 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8 + 0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + cp1_smi_pins: cp1-smi-pins { + marvell,pins = < 27 28 >; + marvell,function = <8>; + }; }; &ap_spi0 { |