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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-03-07 14:32:42 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-03-07 14:32:42 +0100
commitde4fdfc1f22d70c23be5443dafacb8163023f9b1 (patch)
tree47c20593a6d3c9f1a558f0c7590cd0458ed09a99 /arch/arm/cpu
parentdd1e8583ee533a349c03ed4d75446898fe8dbac6 (diff)
parentf940c72e16f7bdebaaed79b290c1bcb6dc015053 (diff)
Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/arm720t/tegra-common/cpu.c5
-rw-r--r--arch/arm/cpu/arm720t/tegra124/cpu.c4
2 files changed, 4 insertions, 5 deletions
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 2c5cd63917..168f525ec7 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -378,8 +378,7 @@ void clock_enable_coresight(int enable)
void halt_avp(void)
{
for (;;) {
- writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
- | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
- FLOW_CTLR_HALT_COP_EVENTS);
+ writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
+ FLOW_CTLR_HALT_COP_EVENTS);
}
}
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
index c03aaf17e9..97f5928bd7 100644
--- a/arch/arm/cpu/arm720t/tegra124/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -252,8 +252,8 @@ void start_cpu(u32 reset_vector)
tegra124_init_clocks();
/* Set power-gating timer multiplier */
- clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
- setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+ writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
+ &pmc->pmc_pwrgate_timer_mult);
enable_cpu_power_rail();
enable_cpu_clocks();