diff options
| author | Simon Glass <sjg@chromium.org> | 2011-09-01 14:21:09 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-09-13 12:52:29 -0700 |
| commit | 404cd8377fc3f334ab037d590af70a6eb43cff49 (patch) | |
| tree | 35d52a1e29aaad5c733fa981ce994d1fbbb19ded /arch/arm/cpu | |
| parent | 9a10befd96a950d643228fb536f7af898219fa49 (diff) | |
tegra: Rename is_tegra2_processor_reset
Change tegra2 to tegra to make it more generic.
BUG=chromium-os:19004
TEST=build and boot on Seaboard
Change-Id: Iad6de3bb6cc6031167862054b78a57f66dea9cd5
Reviewed-on: http://gerrit.chromium.org/gerrit/7127
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/ap20.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/clock.c | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c index 7eae670522..58405d49af 100644 --- a/arch/arm/cpu/armv7/tegra-common/ap20.c +++ b/arch/arm/cpu/armv7/tegra-common/ap20.c @@ -42,7 +42,7 @@ struct clk_pll_table { }; /* ~0=uninitialized/unknown, 0=false, 1=true */ -uint32_t is_tegra2_processor_reset = 0xffffffff; +uint32_t is_tegra_processor_reset = 0xffffffff; /* * Timing tables for each SOC for all four oscillator options. @@ -386,7 +386,7 @@ void tegra_start(void) /* FIXME: should have ap20's L2 disabled too? */ - /* Init is_tegra2_processor_reset */ - is_tegra2_processor_reset = check_is_tegra2_processor_reset(); + /* Init is_tegra_processor_reset */ + is_tegra_processor_reset = check_is_tegra_processor_reset(); } diff --git a/arch/arm/cpu/armv7/tegra-common/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c index fd5393086f..d14fb5e002 100644 --- a/arch/arm/cpu/armv7/tegra-common/clock.c +++ b/arch/arm/cpu/armv7/tegra-common/clock.c @@ -900,7 +900,7 @@ int clock_verify(void) return 0; } -uint32_t check_is_tegra2_processor_reset(void) +uint32_t check_is_tegra_processor_reset(void) { u32 base_reg; struct clk_pll *pll; |