diff options
| author | Bernie Thompson <bhthompson@chromium.org> | 2011-12-02 10:28:30 -0800 |
|---|---|---|
| committer | Gerrit <chrome-bot@google.com> | 2011-12-02 15:24:41 -0800 |
| commit | 28baa5606172c45730b507f4c6047718f7a85d6b (patch) | |
| tree | 81c8234723690f2956da4fb37e9448fb760cb93a /arch/arm/cpu | |
| parent | dbd0840a39a15a950869901dd9668951fd35d01a (diff) | |
Adjust pllx_set_rate to remove delay
This is using the latest patch recommendation from Dilan at Nvidia, we adjust
the ordering to clear bypass earlier and remove the delay.
This patch was run successfully for over 2000 reboots.
BUG=chrome-os-partner:6145
TEST=Manual
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Change-Id: I9ef2f12d5c8abae86791f50b0f5e0e5a4249d947
Reviewed-on: https://gerrit.chromium.org/gerrit/12385
Reviewed-by: Micah Catlin <micahc@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra-common/ap20.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c index 913d8aaa77..5d1f6045f8 100644 --- a/arch/arm/cpu/armv7/tegra-common/ap20.c +++ b/arch/arm/cpu/armv7/tegra-common/ap20.c @@ -178,10 +178,11 @@ static int pllx_set_rate(struct clk_pll *pll , u32 divn, u32 divm, u32 divp, u32 reg; reg = readl(&pll->pll_base); - /* Set m, n and p to PLLX_BASE */ + /* Set m, n and p to PLLX_BASE and clear bypass */ bf_update(PLL_DIVM, reg, divm); bf_update(PLL_DIVN, reg, divn); bf_update(PLL_DIVP, reg, divp); + bf_update(PLL_BYPASS, reg, 0); writel(reg, &pll->pll_base); /* Set cpcon to PLLX_MISC */ @@ -192,15 +193,7 @@ static int pllx_set_rate(struct clk_pll *pll , u32 divn, u32 divm, u32 divp, /* Enable PLLX if not enabled */ if (!bf_unpack(PLL_ENABLE, reg)) { bf_update(PLL_ENABLE, reg, 1); - bf_update(PLL_BYPASS, reg, 0); writel(reg, &pll->pll_base); - /* - * Wait for 200uS, this is done based on what is done in the - * Linux kernel PLL code for Tegra2, this is being kept here - * for now pending on going stability testing on removing - * or lowering it. - */ - udelay(200); } return 0; |