arm: tegra3: Add pinmux functions

The pinmux functions for Tegra3 are quite different from Tegra2, since
we can adjust the setting for each individual pin. We try to keep the
same top-level interface where possible.

(sjg@chromium.org tidied up for 80cols)

BUG=chromium-os:21033
TEST=build and boot on Seaboard

Change-Id: I5bb109e73dc69c3424fe71978417b3f2b210a540
Reviewed-on: http://gerrit.chromium.org/gerrit/8692
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

2 files changed, 508 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/tegra3/Makefile b/arch/arm/cpu/armv7/tegra3/Makefile
index 1d5c6bc521f..0fe1db2a932 100644
--- a/arch/arm/cpu/armv7/tegra3/Makefile
+++ b/arch/arm/cpu/armv7/tegra3/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	=  $(obj)lib$(SOC).o
 
-COBJS-y	:= board.o sys_info.o
+COBJS-y	:= board.o pinmux.o sys_info.o
 
 COBJS	:= $(COBJS-y)
 
diff --git a/arch/arm/cpu/armv7/tegra3/pinmux.c b/arch/arm/cpu/armv7/tegra3/pinmux.c
new file mode 100644
index 00000000000..8a9f87a1b4c
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra3/pinmux.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra3 pin multiplexing functions */
+
+#include <asm/io.h>
+#include <asm/arch-tegra/bitfield.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+#include <common.h>
+
+struct tegra_pingroup_desc {
+	const char *name;
+	enum pmux_func funcs[4];
+	enum pmux_func func_safe;
+	enum pmux_vddio vddio;
+	enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT	0
+#define PMUX_PULL_SHIFT		2
+#define PMUX_TRISTATE_SHIFT	4
+#define PMUX_TRISTATE_MASK	(1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT		5
+#define PMUX_OD_SHIFT		6
+#define PMUX_LOCK_SHIFT		7
+#define PMUX_IO_RESET_SHIFT	8
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod)	\
+	{						\
+		.vddio = PMUX_VDDIO_ ## vdd,		\
+		.funcs = {				\
+			PMUX_FUNC_ ## f0,		\
+			PMUX_FUNC_ ## f1,		\
+			PMUX_FUNC_ ## f2,		\
+			PMUX_FUNC_ ## f3,		\
+		},					\
+		.func_safe = PMUX_FUNC_RSVD,		\
+		.io = PMUX_PIN_ ## iod,			\
+	}
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+	PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+	/*  NAME	VDD	f0	f1	f2	f3	fSafe	io */
+	PINI(ULPI_DATA0,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA1,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA2,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA3,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA4,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA5,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA6,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_DATA7,  BB,	   SPI2,	HSI,	   UARTA,   ULPI),
+	PINI(ULPI_CLK,	  BB,	   SPI1,	RSVD,	   UARTD,   ULPI),
+	PINI(ULPI_DIR,	  BB,	   SPI1,	RSVD,	   UARTD,   ULPI),
+	PINI(ULPI_NXT,	  BB,	   SPI1,	RSVD,	   UARTD,   ULPI),
+	PINI(ULPI_STP,	  BB,	   SPI1,	RSVD,	   UARTD,   ULPI),
+	PINI(DAP3_FS,	  BB,	   I2S2,	RSVD1,	   DISPA,   DISPB),
+	PINI(DAP3_DIN,	  BB,	   I2S2,	RSVD1,	   DISPA,   DISPB),
+	PINI(DAP3_DOUT,	  BB,	   I2S2,	RSVD1,	   DISPA,   DISPB),
+	PINI(DAP3_SCLK,	  BB,	   I2S2,	RSVD1,	   DISPA,   DISPB),
+	PINI(GPIO_PV0,	  BB,	   RSVD,	RSVD,	   RSVD,    RSVD),
+	PINI(GPIO_PV1,	  BB,	   RSVD,	RSVD,	   RSVD,    RSVD),
+	PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,	RSVD1,	   RSVD2,   BAD),
+	PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,	RSVD1,	   RSVD2,   BAD),
+	PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,	RSVD1,	   UARTE,   BAD),
+	PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,	RSVD1,	   UARTE,   BAD),
+	PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,	RSVD1,	   UARTE,   BAD),
+	PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,	RSVD1,	   UARTE,   BAD),
+	PINI(GPIO_PV2,	  SDMMC1,  OWR,		RSVD1,	   RSVD2,   RSVD3),
+	PINI(GPIO_PV3,	  SDMMC1,  BAD,		RSVD1,	   RSVD2,   RSVD3),
+	PINI(CLK2_OUT,	  SDMMC1,  EXTPERIPH2,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(CLK2_REQ,	  SDMMC1,  DAP,		RSVD1,	  RSVD2,    RSVD3),
+	PINO(LCD_PWR1,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_PWR2,	  LCD,	   DISPA,	DISPB,	  SPI5,     BAD),
+	PINO(LCD_SDIN,	  LCD,	   DISPA,	DISPB,	  SPI5,     RSVD),
+	PINO(LCD_SDOUT,	  LCD,	   DISPA,	DISPB,	  SPI5,     BAD),
+	PINO(LCD_WR_N,	  LCD,	   DISPA,	DISPB,	  SPI5,     BAD),
+	PINO(LCD_CS0_N,	  LCD,	   DISPA,	DISPB,	  SPI5,     RSVD),
+	PINO(LCD_DC0,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_SCK,	  LCD,	   DISPA,	DISPB,	  SPI5,     BAD),
+	PINO(LCD_PWR0,	  LCD,	   DISPA,	DISPB,	  SPI5,     BAD),
+	PINO(LCD_PCLK,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_DE,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_HSYNC,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_VSYNC,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D0,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D1,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D2,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D3,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D4,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D5,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D6,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D7,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D8,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D9,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D10,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D11,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D12,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D13,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D14,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D15,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D16,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D17,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D18,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D19,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D20,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D21,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D22,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_D23,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_CS1_N,	  LCD,	   DISPA,	DISPB,	  SPI5,     RSVD2),
+	PINO(LCD_M1,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINO(LCD_DC1,	  LCD,	   DISPA,	DISPB,	  RSVD1,    RSVD2),
+	PINI(HDMI_INT,	  LCD,	   RSVD,	RSVD,	   RSVD,    RSVD),
+	PINI(DDC_SCL,	  LCD,	   I2C4,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(DDC_SDA,	  LCD,	   I2C4,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(CRT_HSYNC,	  LCD,	   CRT,		RSVD1,	   RSVD2,   RSVD3),
+	PINI(CRT_VSYNC,	  LCD,	   CRT,		RSVD1,	   RSVD2,   RSVD3),
+	PINI(VI_D0,	  VI,	   BAD,		RSVD1,	   VI,      RSVD2),
+	PINI(VI_D1,	  VI,	   BAD,		SDMMC2,	   VI,      RSVD1),
+	PINI(VI_D2,	  VI,	   BAD,		SDMMC2,	   VI,      RSVD1),
+	PINI(VI_D3,	  VI,	   BAD,		SDMMC2,	   VI,      RSVD1),
+	PINI(VI_D4,	  VI,	   BAD,		SDMMC2,	   VI,      RSVD1),
+	PINI(VI_D5,	  VI,	   BAD,		SDMMC2,	   VI,      RSVD1),
+	PINI(VI_D6,	  VI,	   BAD,		SDMMC2,	   VI,      RSVD1),
+	PINI(VI_D7,	  VI,	   BAD,		SDMMC2,	   VI,      RSVD1),
+	PINI(VI_D8,	  VI,	   BAD,		SDMMC2,	   VI,      RSVD1),
+	PINI(VI_D9,	  VI,	   BAD,		SDMMC2,	   VI,      RSVD1),
+	PINI(VI_D10,	  VI,	   BAD,		RSVD1,	   VI,      RSVD2),
+	PINI(VI_D11,	  VI,	   BAD,		RSVD1,	   VI,      RSVD2),
+	PINI(VI_PCLK,	  VI,	   RSVD1,	SDMMC2,	   VI,      RSVD2),
+	PINI(VI_MCLK,	  VI,	   VI,		BAD,	   BAD,     BAD),
+	PINI(VI_VSYNC,	  VI,	   BAD,		RSVD1,	   VI,      RSVD2),
+	PINI(VI_HSYNC,	  VI,	   BAD,		RSVD1,	   VI,      RSVD2),
+	PINI(UART2_RXD,	  UART,	   IRDA,	SPDIF,	   UARTA,   SPI4),
+	PINI(UART2_TXD,	  UART,	   IRDA,	SPDIF,	   UARTA,   SPI4),
+	PINI(UART2_RTS_N, UART,	   UARTA,	UARTB,	   GMI,     SPI4),
+	PINI(UART2_CTS_N, UART,	   UARTA,	UARTB,	   GMI,     SPI4),
+	PINI(UART3_TXD,	  UART,	   UARTC,	RSVD1,	   GMI,     RSVD2),
+	PINI(UART3_RXD,	  UART,	   UARTC,	RSVD1,	   GMI,     RSVD2),
+	PINI(UART3_CTS_N, UART,	   UARTC,	RSVD1,	   GMI,     RSVD2),
+	PINI(UART3_RTS_N, UART,	   UARTC,	PWM0,	   GMI,     RSVD2),
+	PINI(GPIO_PU0,	  UART,	   OWR,		UARTA,	   GMI,     RSVD1),
+	PINI(GPIO_PU1,	  UART,	   RSVD1,	UARTA,	   GMI,     RSVD2),
+	PINI(GPIO_PU2,	  UART,	   RSVD1,	UARTA,	   GMI,     RSVD2),
+	PINI(GPIO_PU3,	  UART,	   PWM0,	UARTA,	   GMI,     RSVD1),
+	PINI(GPIO_PU4,	  UART,	   PWM1,	UARTA,	   GMI,     RSVD1),
+	PINI(GPIO_PU5,	  UART,	   PWM2,	UARTA,	   GMI,     RSVD1),
+	PINI(GPIO_PU6,	  UART,	   PWM3,	UARTA,	   GMI,     RSVD1),
+	PINI(GEN1_I2C_SDA, UART,   I2C1,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(GEN1_I2C_SCL, UART,   I2C1,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(DAP4_FS,	  UART,	   I2S3,	RSVD1,	   GMI,     RSVD2),
+	PINI(DAP4_DIN,	  UART,	   I2S3,	RSVD1,	   GMI,     RSVD2),
+	PINI(DAP4_DOUT,	  UART,	   I2S3,	RSVD1,	   GMI,     RSVD2),
+	PINI(DAP4_SCLK,	  UART,	   I2S3,	RSVD1,	   GMI,     RSVD2),
+	PINI(CLK3_OUT,	  UART,	   EXTPERIPH3,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(CLK3_REQ,	  UART,	   DEV3,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(GMI_WP_N,	  GMI,	   RSVD1,	NAND,	   GMI,     GMI_ALT),
+	PINI(GMI_IORDY,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_WAIT,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_ADV_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_CLK,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_CS0_N,	  GMI,	   RSVD1,	NAND,	   GMI,     BAD),
+	PINI(GMI_CS1_N,	  GMI,	   RSVD1,	NAND,	   GMI,     DTV),
+	PINI(GMI_CS2_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_CS3_N,	  GMI,	   RSVD1,	NAND,	   GMI,     GMI_ALT),
+	PINI(GMI_CS4_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_CS6_N,	  GMI,	   NAND,	NAND_ALT,  GMI,     SATA),
+	PINI(GMI_CS7_N,	  GMI,	   NAND,	NAND_ALT,  GMI,     GMI_ALT),
+	PINI(GMI_AD0,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD1,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD2,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD3,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD4,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD5,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD6,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD7,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD8,	  GMI,	   PWM0,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD9,	  GMI,	   PWM1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD10,	  GMI,	   PWM2,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD11,	  GMI,	   PWM3,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD12,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD13,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD14,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_AD15,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD2),
+	PINI(GMI_A16,	  GMI,	   UARTD,	SPI4,	   GMI,     GMI_ALT),
+	PINI(GMI_A17,	  GMI,	   UARTD,	SPI4,	   GMI,     BAD),
+	PINI(GMI_A18,	  GMI,	   UARTD,	SPI4,	   GMI,     BAD),
+	PINI(GMI_A19,	  GMI,	   UARTD,	SPI4,	   GMI,     RSVD3),
+	PINI(GMI_WR_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD3),
+	PINI(GMI_OE_N,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD3),
+	PINI(GMI_DQS,	  GMI,	   RSVD1,	NAND,	   GMI,     RSVD3),
+	PINI(GMI_RST_N,	  GMI,	   NAND,	NAND_ALT,  GMI,     RSVD3),
+	PINI(GEN2_I2C_SCL, GMI,	   I2C2,	BAD,	   GMI,     RSVD3),
+	PINI(GEN2_I2C_SDA, GMI,	   I2C2,	BAD,	   GMI,     RSVD3),
+	PINI(SDMMC4_CLK,  SDMMC4,  BAD,		NAND,	   GMI,     SDMMC4),
+	PINI(SDMMC4_CMD,  SDMMC4,  I2C3,	NAND,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT0, SDMMC4,  UARTE,	SPI3,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT1, SDMMC4,  UARTE,	SPI3,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT2, SDMMC4,  UARTE,	SPI3,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT3, SDMMC4,  UARTE,	SPI3,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT4, SDMMC4,  I2C3,	I2S4,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT5, SDMMC4,  VGP3,	I2S4,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT6, SDMMC4,  VGP4,	I2S4,	   GMI,     SDMMC4),
+	PINI(SDMMC4_DAT7, SDMMC4,  VGP5,	I2S4,	   GMI,     SDMMC4),
+	PINI(SDMMC4_RST_N, SDMMC4, VGP6,	RSVD1,	   RSVD2,   POPSDMMC4),
+	PINI(CAM_MCLK,	  CAM,	   VI,		BAD,	   VI_ALT2, POPSDMMC4),
+	PINI(GPIO_PCC1,	  CAM,	   I2S4,	RSVD1,	   RSVD2,   POPSDMMC4),
+	PINI(GPIO_PBB0,	  CAM,	   I2S4,	RSVD1,	   RSVD2,   POPSDMMC4),
+	PINI(CAM_I2C_SCL, CAM,	   BAD,		I2C3,	   RSVD2,   POPSDMMC4),
+	PINI(CAM_I2C_SDA, CAM,	   BAD,		I2C3,	   RSVD2,   POPSDMMC4),
+	PINI(GPIO_PBB3,	  CAM,	   VGP3,	DISPA,	   DISPB,   POPSDMMC4),
+	PINI(GPIO_PBB4,	  CAM,	   VGP4,	DISPA,	   DISPB,   POPSDMMC4),
+	PINI(GPIO_PBB5,	  CAM,	   VGP5,	DISPA,	   DISPB,   POPSDMMC4),
+	PINI(GPIO_PBB6,	  CAM,	   VGP6,	DISPA,	   DISPB,   POPSDMMC4),
+	PINI(GPIO_PBB7,	  CAM,	   I2S4,	RSVD1,	   RSVD2,   POPSDMMC4),
+	PINI(GPIO_PCC2,	  CAM,	   I2S4,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(JTAG_RTCK,	  SYS,	   RTCK,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(PWR_I2C_SCL, SYS,	   I2CPWR,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(PWR_I2C_SDA, SYS,	   I2CPWR,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(KB_ROW0,	  SYS,	   KBC,		BAD,	   RSVD2,   RSVD3),
+	PINI(KB_ROW1,	  SYS,	   KBC,		BAD,	   RSVD2,   RSVD3),
+	PINI(KB_ROW2,	  SYS,	   KBC,		BAD,	   RSVD2,   RSVD3),
+	PINI(KB_ROW3,	  SYS,	   KBC,		BAD,	   RSVD2,   BAD),
+	PINI(KB_ROW4,	  SYS,	   KBC,		BAD,	   TRACE,   RSVD3),
+	PINI(KB_ROW5,	  SYS,	   KBC,		BAD,	   TRACE,   OWR),
+	PINI(KB_ROW6,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_ROW7,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_ROW8,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_ROW9,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_ROW10,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_ROW11,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_ROW12,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_ROW13,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_ROW14,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_ROW15,	  SYS,	   KBC,		BAD,	   SDMMC2,  BAD),
+	PINI(KB_COL0,	  SYS,	   KBC,		BAD,	   TRACE,   BAD),
+	PINI(KB_COL1,	  SYS,	   KBC,		BAD,	   TRACE,   BAD),
+	PINI(KB_COL2,	  SYS,	   KBC,		BAD,	   TRACE,   RSVD),
+	PINI(KB_COL3,	  SYS,	   KBC,		BAD,	   TRACE,   RSVD),
+	PINI(KB_COL4,	  SYS,	   KBC,		BAD,	   TRACE,   RSVD),
+	PINI(KB_COL5,	  SYS,	   KBC,		BAD,	   TRACE,   RSVD),
+	PINI(KB_COL6,	  SYS,	   KBC,		BAD,	   TRACE,   BAD),
+	PINI(KB_COL7,	  SYS,	   KBC,		BAD,	   TRACE,   BAD),
+	PINI(CLK_32K_OUT, SYS,	   BLINK,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(SYS_CLK_REQ, SYS,	   SYSCLK,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(CORE_PWR_REQ, SYS,	   RSVD,	RSVD,	   RSVD,    RSVD),
+	PINI(CPU_PWR_REQ, SYS,	   RSVD,	RSVD,	   RSVD,    RSVD),
+	PINI(PWR_INT_N,	  SYS,	   RSVD,	RSVD,	   RSVD,    RSVD),
+	PINI(CLK_32K_IN,  SYS,	   RSVD,	RSVD,	   RSVD,    RSVD),
+	PINI(OWR,	  SYS,	   OWR,		RSVD,	   RSVD,    RSVD),
+	PINI(DAP1_FS,	  AUDIO,   I2S0,	HDA,	   GMI,     SDMMC2),
+	PINI(DAP1_DIN,	  AUDIO,   I2S0,	HDA,	   GMI,     SDMMC2),
+	PINI(DAP1_DOUT,	  AUDIO,   I2S0,	HDA,	   GMI,     SDMMC2),
+	PINI(DAP1_SCLK,	  AUDIO,   I2S0,	HDA,	   GMI,     SDMMC2),
+	PINI(CLK1_REQ,	  AUDIO,   DAP,		HDA,	   RSVD2,   RSVD3),
+	PINI(CLK1_OUT,	  AUDIO,   EXTPERIPH1,	RSVD1,	   RSVD2,   RSVD3),
+	PINI(SPDIF_IN,	  AUDIO,   SPDIF,	HDA,	   BAD,     DAPSDMMC2),
+	PINI(SPDIF_OUT,	  AUDIO,   SPDIF,	RSVD1,	   BAD,     DAPSDMMC2),
+	PINI(DAP2_FS,	  AUDIO,   I2S1,	HDA,	   RSVD2,   GMI),
+	PINI(DAP2_DIN,	  AUDIO,   I2S1,	HDA,	   RSVD2,   GMI),
+	PINI(DAP2_DOUT,	  AUDIO,   I2S1,	HDA,	   RSVD2,   GMI),
+	PINI(DAP2_SCLK,	  AUDIO,   I2S1,	HDA,	   RSVD2,   GMI),
+	PINI(SPI2_MOSI,	  AUDIO,   SPI6,	SPI2,	   BAD,     GMI),
+	PINI(SPI2_MISO,	  AUDIO,   SPI6,	SPI2,	   BAD,     GMI),
+	PINI(SPI2_CS0_N,  AUDIO,   SPI6,	SPI2,	   BAD,     GMI),
+	PINI(SPI2_SCK,	  AUDIO,   SPI6,	SPI2,	   BAD,     GMI),
+	PINI(SPI1_MOSI,	  AUDIO,   SPI2,	SPI1,	   BAD,     GMI),
+	PINI(SPI1_SCK,	  AUDIO,   SPI2,	SPI1,	   BAD,     GMI),
+	PINI(SPI1_CS0_N,  AUDIO,   SPI2,	SPI1,	   BAD,     GMI),
+	PINI(SPI1_MISO,	  AUDIO,   BAD,		SPI1,	   BAD,     RSVD3),
+	PINI(SPI2_CS1_N,  AUDIO,   BAD,		SPI2,	   BAD,     BAD),
+	PINI(SPI2_CS2_N,  AUDIO,   BAD,		SPI2,	   BAD,     BAD),
+	PINI(SDMMC3_CLK,  SDMMC3,  UARTA,	PWM2,	   SDMMC3,  BAD),
+	PINI(SDMMC3_CMD,  SDMMC3,  UARTA,	PWM3,	   SDMMC3,  BAD),
+	PINI(SDMMC3_DAT0, SDMMC3,  RSVD0,	RSVD1,	   SDMMC3,  BAD),
+	PINI(SDMMC3_DAT1, SDMMC3,  RSVD0,	RSVD1,	   SDMMC3,  BAD),
+	PINI(SDMMC3_DAT2, SDMMC3,  RSVD0,	PWM1,	   SDMMC3,  BAD),
+	PINI(SDMMC3_DAT3, SDMMC3,  RSVD0,	PWM0,	   SDMMC3,  BAD),
+	PINI(SDMMC3_DAT4, SDMMC3,  PWM1,	BAD,	   SDMMC3,  BAD),
+	PINI(SDMMC3_DAT5, SDMMC3,  PWM0,	BAD,	   SDMMC3,  BAD),
+	PINI(SDMMC3_DAT6, SDMMC3,  SPDIF,	BAD,	   SDMMC3,  BAD),
+	PINI(SDMMC3_DAT7, SDMMC3,  SPDIF,	BAD,	   SDMMC3,  BAD),
+	PINI(PEX_L0_PRSNT_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(PEX_L0_RST_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(PEX_L0_CLKREQ_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(PEX_WAKE_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(PEX_L1_PRSNT_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(PEX_L1_RST_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(PEX_L1_CLKREQ_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(PEX_L2_PRSNT_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(PEX_L2_RST_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(PEX_L2_CLKREQ_N,	PEXCTL,   PCIE,	HDA,	   RSVD2,   RSVD3),
+	PINI(HDMI_CEC,		SYS,      CEC,	RSVD1,	   RSVD2,   RSVD3),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *tri = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin */
+	assert(pmux_pingrp_isvalid(pin));
+
+	reg = readl(tri);
+	if (enable)
+		reg |= PMUX_TRISTATE_MASK;
+	else
+		reg &= ~PMUX_TRISTATE_MASK;
+	writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+	pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pull = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and pupd */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_pupd_isvalid(pupd));
+
+	reg = readl(pull);
+	reg &= ~(0x3 << PMUX_PULL_SHIFT);
+	reg |= (pupd << PMUX_PULL_SHIFT);
+	writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *muxctl = &pmt->pmt_ctl[pin];
+	int i, mux = -1;
+	u32 reg;
+
+	/* Error check on pin and func */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_func_isvalid(func));
+
+	/* Handle special values */
+	if (func == PMUX_FUNC_SAFE)
+		func = tegra_soc_pingroups[pin].func_safe;
+
+	if (func & PMUX_FUNC_RSVD) {
+		mux = func & 0x3;
+	} else {
+		/* Search for the appropriate function */
+		for (i = 0; i < 4; i++) {
+			if (tegra_soc_pingroups[pin].funcs[i] == func) {
+				mux = i;
+				break;
+			}
+		}
+	}
+	assert(mux != -1);
+
+	reg = readl(muxctl);
+	reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+	reg |= (mux << PMUX_MUXCTL_SHIFT);
+	writel(reg, muxctl);
+
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_io = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and io */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_io_isvalid(io));
+
+	reg = readl(pin_io);
+	reg &= ~(0x1 << PMUX_IO_SHIFT);
+	reg |= (io & 0x1) << PMUX_IO_SHIFT;
+	writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_lock = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and lock */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_lock_isvalid(lock));
+
+	if (lock == PMUX_PIN_LOCK_DEFAULT)
+		return 0;
+
+	reg = readl(pin_lock);
+	reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+	if (lock == PMUX_PIN_LOCK_ENABLE)
+		reg |= (0x1 << PMUX_LOCK_SHIFT);
+	writel(reg, pin_lock);
+
+	return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_od = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and od */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_od_isvalid(od));
+
+	if (od == PMUX_PIN_OD_DEFAULT)
+		return 0;
+
+	reg = readl(pin_od);
+	reg &= ~(0x1 << PMUX_OD_SHIFT);
+	if (od == PMUX_PIN_OD_ENABLE)
+		reg |= (0x1 << PMUX_OD_SHIFT);
+	writel(reg, pin_od);
+
+	return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+				enum pmux_pin_ioreset ioreset)
+{
+	struct pmux_tri_ctlr *pmt =
+			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+	u32 reg;
+
+	/* Error check on pin and ioreset */
+	assert(pmux_pingrp_isvalid(pin));
+	assert(pmux_pin_ioreset_isvalid(ioreset));
+
+	if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+		return 0;
+
+	reg = readl(pin_ioreset);
+	reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+	if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+		reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+	writel(reg, pin_ioreset);
+
+	return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+	enum pmux_pingrp pin = config->pingroup;
+
+	pinmux_set_func(pin, config->func);
+	pinmux_set_pullupdown(pin, config->pull);
+	pinmux_set_tristate(pin, config->tristate);
+	pinmux_set_io(pin, config->io);
+	pinmux_set_lock(pin, config->lock);
+	pinmux_set_od(pin, config->od);
+	pinmux_set_ioreset(pin, config->ioreset);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		pinmux_config_pingroup(&config[i]);
+}