tegra: Move tegra2 files into tegra-common

This code is required for Tegra30 also, so we move it into a common
directory.

BUG=chromium-os:19004
TEST=build and boot on Seaboard

Change-Id: I9af13892861f54c0d7da6d4f9ee0715bc5ab6357
Reviewed-on: http://gerrit.chromium.org/gerrit/7124
Reviewed-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

10 files changed, 58 insertions, 121 deletions

diff --git a/arch/arm/cpu/armv7/tegra-common/Makefile b/arch/arm/cpu/armv7/tegra-common/Makefile
new file mode 100644
index 0000000000..5c39030485
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra-common/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CFLAGS_arch/arm/cpu/armv7/tegra-common/ap20.o += -march=armv4t
+CFLAGS_arch/arm/cpu/armv7/tegra-common/clock.o += -march=armv4t
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)libtegra-common.o
+
+SOBJS-y	:= lowlevel_init.o
+COBJS-y	:= ap20.o clock.o timer.o
+
+SOBJS	:= $(SOBJS-y)
+COBJS	:= $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c
index f9aa610aec..7eae670522 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra-common/ap20.c
@@ -21,7 +21,6 @@
 * MA 02111-1307 USA
 */
 
-#include "ap20.h"
 #include <asm/io.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch/bitfield.h>
@@ -32,6 +31,7 @@
 #include <asm/arch/scu.h>
 #include <common.h>
 #include <asm/arch/warmboot.h>
+#include <asm/arch-tegra/ap20.h>
 #include "../../../../../board/nvidia/common/board.h"
 
 struct clk_pll_table {
diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c
index fd5393086f..fd5393086f 100644
--- a/arch/arm/cpu/armv7/tegra2/clock.c
+++ b/arch/arm/cpu/armv7/tegra-common/clock.c
diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra-common/lowlevel_init.S
index 333f1b7c8e..333f1b7c8e 100644
--- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/tegra-common/lowlevel_init.S
diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/armv7/tegra-common/timer.c
index 552c9adcbb..552c9adcbb 100644
--- a/arch/arm/cpu/armv7/tegra2/timer.c
+++ b/arch/arm/cpu/armv7/tegra-common/timer.c
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile
index 5812da6cac..4e0b22f4a6 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -26,17 +26,14 @@
 # The AVP is ARMv4T architecture so we must use special compiler
 # flags for any files it might use.
 
-CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t
-CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t
 CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t
 
 include $(TOPDIR)/config.mk
 
 LIB	=  $(obj)lib$(SOC).o
 
-SOBJS-y	:= lowlevel_init.o
-COBJS-y	:= ap20.o board.o clock.o display.o pinmux.o power.o pwfm.o \
-		sys_info.o timer.o
+SOBJS-y	:=
+COBJS-y	:= board.o display.o pinmux.o power.o pwfm.o sys_info.o
 
 COBJS-$(CONFIG_TEGRA2_LP0) += warmboot.o
 COBJS-$(CONFIG_TEGRA2_LP0) += warmboot_avp.o
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/cpu/armv7/tegra2/ap20.h
deleted file mode 100644
index 4f7d7ce714..0000000000
--- a/arch/arm/cpu/armv7/tegra2/ap20.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2010-2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <asm/types.h>
-
-/* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY (300)
-#define IO_STABILIZATION_DELAY	(1000)
-
-#define NVBL_PLLP_KHZ	(216000)
-
-#define PLLX_ENABLED		(1 << 30)
-#define CCLK_BURST_POLICY	0x20008888
-#define SUPER_CCLK_DIVIDER	0x80000000
-
-/* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ)  ((((REF) * 2) / FREQ) - 2)
-
-/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG)  (((REF) * 2) / (REG + 2))
-
-/* AVP/CPU ID */
-#define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0             0x0
-
-#define CORESIGHT_UNLOCK	0xC5ACCE55;
-
-/* AP20-Specific Base Addresses */
-
-/* AP20 Base physical address of SDRAM. */
-#define AP20_BASE_PA_SDRAM      0x00000000
-/* AP20 Base physical address of internal SRAM. */
-#define AP20_BASE_PA_SRAM       0x40000000
-/* AP20 Size of internal SRAM (256KB). */
-#define AP20_BASE_PA_SRAM_SIZE  0x00040000
-/* AP20 Base physical address of flash. */
-#define AP20_BASE_PA_NOR_FLASH  0xD0000000
-/* AP20 Base physical address of boot information table. */
-#define AP20_BASE_PA_BOOT_INFO  AP20_BASE_PA_SRAM
-
-/*
- * Super-temporary stacks for EXTREMELY early startup. The values chosen for
- * these addresses must be valid on ALL SOCs because this value is used before
- * we are able to differentiate between the SOC types.
- *
- * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
- *       stack is placed below the AVP stack. Once the CPU stack has been moved,
- *       the AVP is free to use the IRAM the CPU stack previously occupied if
- *       it should need to do so.
- *
- * NOTE: In multi-processor CPU complex configurations, each processor will have
- *       its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
- *       limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
- *       stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
- *       CPU.
- */
-
-/* Common AVP early boot stack limit */
-#define AVP_EARLY_BOOT_STACK_LIMIT	\
-	(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
-/* Common AVP early boot stack size */
-#define AVP_EARLY_BOOT_STACK_SIZE	0x1000
-/* Common CPU early boot stack limit */
-#define CPU_EARLY_BOOT_STACK_LIMIT	\
-	(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
-/* Common CPU early boot stack size */
-#define CPU_EARLY_BOOT_STACK_SIZE	0x1000
-
-#define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
-#define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
-#define CSITE_CPU_DBG1_LAR		(NV_PA_CSITE_BASE + 0x12FB0)
-
-#define FLOW_CTLR_HALT_COP_EVENTS	(NV_PA_FLOW_BASE + 4)
-#define FLOW_MODE_STOP			2
-#define HALT_COP_EVENT_JTAG		(1 << 28)
-#define HALT_COP_EVENT_IRQ_1		(1 << 11)
-#define HALT_COP_EVENT_FIQ_1		(1 << 9)
-
-/* Called by the ARM7 to start up the Cortex-A9, and by the A9 to do init */
-void tegra_start(void);
-
-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-int ap20_cpu_is_cortexa9(void);
-
-/**
- * Init the PLLX which clocks the CPU.
- *
- * The 'slow' option is used when the CPU voltage has not yet been increased
- * to allow running at full speed.
- *
- * @param slow	1 to run in safe/slow mode, 0 to run at full speed
- */
-void ap20_init_pllx(int slow);
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
index 0d71b6157f..cc3d8dd86f 100644
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include "ap20.h"
+#include <asm/arch-tegra/ap20.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch/pmc.h>
diff --git a/arch/arm/cpu/armv7/tegra2/warmboot.c b/arch/arm/cpu/armv7/tegra2/warmboot.c
index 8c2ddf7cdb..3ee72c4ec1 100644
--- a/arch/arm/cpu/armv7/tegra2/warmboot.c
+++ b/arch/arm/cpu/armv7/tegra2/warmboot.c
@@ -35,7 +35,7 @@
 #include <asm/arch/gp_padctrl.h>
 #include <asm/arch/warmboot.h>
 #include <asm/arch/sdram_param.h>
-#include "ap20.h"
+#include <asm/arch-tegra/ap20.h>
 
 #define BCT_OFFSET		0x100		/* BCT starts at 0x100 */
 #define BCT_SDRAM_PARAMS_OFFSET	(BCT_OFFSET + 0x88)
diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.c b/arch/arm/cpu/armv7/tegra2/warmboot_avp.c
index 4a22caf06b..a3db98907f 100644
--- a/arch/arm/cpu/armv7/tegra2/warmboot_avp.c
+++ b/arch/arm/cpu/armv7/tegra2/warmboot_avp.c
@@ -30,7 +30,7 @@
 #include <asm/arch/tegra.h>
 #include <asm/arch/flow.h>
 #include <asm/arch/warmboot.h>
-#include "ap20.h"
+#include <asm/arch-tegra/ap20.h>
 #include "warmboot_avp.h"
 
 #define DEBUG_RESET_CORESIGHT