diff options
| author | Che-Liang Chiou <clchiou@chromium.org> | 2011-07-02 17:27:28 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-29 10:58:44 -0700 |
| commit | 12f3d7fc17ee799dee85e37669de6a53abb10f88 (patch) | |
| tree | d79da41a42e724d144d176006ee5476f6f04ebab /arch/arm/cpu | |
| parent | d056165754bda579dd93cf12628e2a2afcc68709 (diff) | |
tegra2: logging whether it is a cold boot or not
The second stage firmware has to know the system is booted up after a
first stage u-boot.
BUG=chromium-os:17056
TEST=manual
1. Do cold boot
2. Then do a warm boot (run "go 0xe08000")
3. Meanwhile you should observe that _IS_TEGRA2_COLD_BOOT switches
from 0 to 1 (run "md.b" to dump memory content)
Change-Id: I70b155cb2be9566416dbe7ace255cae928f6fc93
Reviewed-on: http://gerrit.chromium.org/gerrit/3602
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/ap20.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/clock.c | 11 |
2 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index abcfa977ab8..75fdf7c22f5 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -41,6 +41,9 @@ struct clk_pll_table { u8 cpcon; }; +/* ~0=uninitialized/unknown, 0=false, 1=true */ +int is_tegra2_cold_boot = 0xffffffff; + /* * Timing tables for each SOC for all four oscillator options. */ @@ -383,5 +386,8 @@ void tegra2_start(void) "mcr p15, 0, r0, c1, c0, 1\n"); /* FIXME: should have ap20's L2 disabled too? */ + + /* Init is_tegra2_cold_boot */ + is_tegra2_cold_boot = check_is_tegra2_cold_boot(); } diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 6af7010993a..a33b0d9da63 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -879,6 +879,17 @@ static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) return 0; } +int check_is_tegra2_cold_boot(void) +{ + u32 base_reg; + struct clk_pll *pll; + + pll = get_pll(CLOCK_ID_PERIPH); + base_reg = readl(&pll->pll_base); + + return (base_reg & bf_mask(PLL_BASE_OVRRIDE)) ? 0 : 1; +} + void common_pll_init(void) { /* |