diff options
author | Tom Rini <trini@ti.com> | 2014-11-24 12:02:12 -0500 |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2014-11-24 12:02:12 -0500 |
commit | dee332ffb735f65ab922118791a583c17bb0b795 (patch) | |
tree | d07bc0821792831aa4baeb27868252c2d32c7738 /arch/arm/cpu | |
parent | 1739564e753bc3a8097f8937a3cbe738bdaaed5d (diff) | |
parent | e7eb277dced570f177d75d56f40219d9dc599ed1 (diff) |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/arm926ejs/mx27/Makefile | 4 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mx27/relocate.S | 51 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/mx5/soc.c | 31 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 38 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 15 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap-common/sata.c | 5 |
9 files changed, 116 insertions, 31 deletions
diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile index 4976bbb89b0..0edf1445fe3 100644 --- a/arch/arm/cpu/arm926ejs/mx27/Makefile +++ b/arch/arm/cpu/arm926ejs/mx27/Makefile @@ -5,3 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y = generic.o reset.o timer.o + +ifndef CONFIG_SPL_BUILD +obj-y += relocate.o +endif diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S new file mode 100644 index 00000000000..0c4b2728895 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S @@ -0,0 +1,51 @@ +/* + * relocate - i.MX27-specific vector relocation + * + * Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> + +/* + * The i.MX27 SoC is very specific with respect to exceptions: it + * does not provide RAM at the high vectors address (0xFFFF0000), + * thus only the low address (0x00000000) is useable; but that is + * in ROM. Therefore, vectors cannot be changed at all. + * + * However, these ROM-based vectors actually just perform indirect + * calls through pointers located in RAM at SoC-specific addresses, + * as follows: + * + * Offset Exception Use by ROM code + * 0x00000000 reset indirect branch to [0x00000014] + * 0x00000004 undefined instruction indirect branch to [0xfffffef0] + * 0x00000008 software interrupt indirect branch to [0xfffffef4] + * 0x0000000c prefetch abort indirect branch to [0xfffffef8] + * 0x00000010 data abort indirect branch to [0xfffffefc] + * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000 + * 0x00000018 IRQ indirect branch to [0xffffff00] + * 0x0000001c FIQ indirect branch to [0xffffff04] + * + * In order to initialize exceptions on i.MX27, we must copy U-Boot's + * indirect (not exception!) vector table into 0xfffffef0..0xffffff04 + * taking care not to copy vectors number 5 (reserved exception). + */ + + .section .text.relocate_vectors,"ax",%progbits + +ENTRY(relocate_vectors) + + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + ldr r1, =32 /* size of vector table */ + add r0, r0, r1 /* skip to indirect table */ + ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */ + ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */ + stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */ + + bx lr + +ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg index 1520bba3fba..83953daf287 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg @@ -1,3 +1,4 @@ +DISPLAYPROGRESS SECTION 0x0 BOOTABLE TAG LAST LOAD 0x1000 spl/u-boot-spl.bin diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index 55510e9cd8f..e7028092a2c 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,3 +1,4 @@ +DISPLAYPROGRESS SECTION 0x0 BOOTABLE TAG LAST LOAD 0x1000 spl/u-boot-spl.bin diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index bb78cb0c848..3f7bf599248 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,3 +1,4 @@ +DISPLAYPROGRESS SECTION 0x0 BOOTABLE TAG LAST LOAD 0x1000 spl/u-boot-spl.bin diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 2d53669c89d..3753c14df39 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -85,37 +85,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif -void set_chipselect_size(int const cs_size) -{ - unsigned int reg; - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - reg = readl(&iomuxc_regs->gpr1); - - switch (cs_size) { - case CS0_128: - reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ - reg |= 0x5; - break; - case CS0_64M_CS1_64M: - reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ - reg |= 0x1B; - break; - case CS0_64M_CS1_32M_CS2_32M: - reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ - reg |= 0x4B; - break; - case CS0_32M_CS1_32M_CS2_32M_CS3_32M: - reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ - reg |= 0x249; - break; - default: - printf("Unknown chip select size: %d\n", cs_size); - break; - } - - writel(reg, &iomuxc_regs->gpr1); -} - #ifdef CONFIG_MX53 void boot_mode_apply(unsigned cfg_val) { diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 6c9c78c11a1..ab7ac3d703e 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -596,6 +596,14 @@ int enable_sata_clock(void) ungate_sata_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); } + +void disable_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} #endif int enable_pcie_clock(void) @@ -673,6 +681,36 @@ void hab_caam_clock_enable(unsigned char enable) } #endif +static void enable_pll3(void) +{ + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + + /* make sure pll3 is enabled */ + if ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { + /* enable pll's power */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, + &anatop->usb1_pll_480_ctrl_set); + writel(0x80, &anatop->ana_misc2_clr); + /* wait for pll lock */ + while ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) + ; + /* disable bypass */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, + &anatop->usb1_pll_480_ctrl_clr); + /* enable pll output */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, + &anatop->usb1_pll_480_ctrl_set); + } +} + +void enable_thermal_clk(void) +{ + enable_pll3(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5fd2a63a1db..5f5f4972010 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -22,6 +22,8 @@ #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> #include <asm/bootm.h> +#include <dm.h> +#include <imx_thermal.h> enum ldo_reg { LDO_ARM, @@ -37,6 +39,19 @@ struct scu_regs { u32 fpga_rev; }; +#if defined(CONFIG_IMX6_THERMAL) +static const struct imx_thermal_plat imx6_thermal_plat = { + .regs = (void *)ANATOP_BASE_ADDR, + .fuse_bank = 1, + .fuse_word = 6, +}; + +U_BOOT_DEVICE(imx6_thermal) = { + .name = "imx_thermal", + .platdata = &imx6_thermal_plat, +}; +#endif + u32 get_nr_cpus(void) { struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index 3b4dd3f5d77..a24baa13377 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -74,6 +74,11 @@ int init_sata(int dev) return ret; } +int reset_sata(int dev) +{ + return 0; +} + /* On OMAP platforms SATA provides the SCSI subsystem */ void scsi_init(void) { |