diff options
| author | Simon Glass <sjg@chromium.org> | 2011-06-08 14:45:10 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-29 10:39:17 -0700 |
| commit | aae9165fc234393fbc794f9f33188c468670b0c8 (patch) | |
| tree | 688ca2b6162883e22b633f85bdf080b927467fc6 /arch/arm/cpu | |
| parent | 2f7a0c97f1d656a8731a1ad570abf8831ce81758 (diff) | |
Add a function to return a clock rate
clock_get_rate() returns the current rate for a clock.
BUG=chromium-os:14082
TEST=build U-Boot
Change-Id: I7796e5c272e5d510d0f361f6e51a59df6a39fe1a
Reviewed-on: http://gerrit.chromium.org/gerrit/2344
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/clock.c | 26 |
1 files changed, 11 insertions, 15 deletions
diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 0abd361af68..275aacc5ac7 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -776,22 +776,20 @@ void reset_cmplx_set_enable(int cpu, int which, int reset) writel(mask, &clkrst->crc_cpu_cmplx_clr); } -/** - * Returns the frequency of the given PLL. This assumes that the PLL is fed - * from the main oscillator. - * - * @param clkid Clock to examine - * @return clock frequency in Hz - */ -static unsigned get_clock_freq(enum clock_id clkid) +unsigned clock_get_rate(enum clock_id clkid) { - struct clk_pll *pll = get_pll(clkid); - u32 base = readl(&pll->pll_base); + struct clk_pll *pll; + u32 base; u32 divm; u64 parent_rate; u64 rate; parent_rate = osc_freq[clock_get_osc_freq()]; + if (clkid == CLOCK_ID_OSC) + return parent_rate; + + pll = get_pll(clkid); + base = readl(&pll->pll_base); rate = parent_rate * bf_unpack(PLL_DIVN, base); divm = bf_unpack(PLL_DIVM, base); if (clkid == CLOCK_ID_USB) @@ -804,11 +802,9 @@ static unsigned get_clock_freq(enum clock_id clkid) void clock_init(void) { - pll_rate[CLOCK_ID_MEMORY] = get_clock_freq(CLOCK_ID_MEMORY); - pll_rate[CLOCK_ID_PERIPH] = get_clock_freq(CLOCK_ID_PERIPH); - /* FIXME: I2C needs CLK_M for CLOCK_ID_OSC */ - /* pll_rate[CLOCK_ID_OSC] = get_clock_freq(CLOCK_ID_PERIPH); */ - pll_rate[CLOCK_ID_OSC] = osc_freq[clock_get_osc_freq()]; + pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); + pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); + pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); |