diff options
| author | Che-Liang Chiou <clchiou@chromium.org> | 2011-07-25 12:18:13 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-29 10:59:10 -0700 |
| commit | b987ec791ede0f8215373c9a88585a9e41566ff0 (patch) | |
| tree | ec0e1b27b2d1e2511a4b6cbc9be8d6aea0fb2ee0 /arch/arm/cpu | |
| parent | 2671be40bc552e404b6df24811c4a951b81d6a52 (diff) | |
CHROMIUM: rename is_cold_boot to is_processor_reset
The predicate function is_cold_boot() is in fact telling you whether we
are booting from a processor reset.
BUG=chrome-os-partner:5100
TEST=build cleanly
Change-Id: I70f56448dd1b327426cf759854c35e20e0b4cfcf
Reviewed-on: http://gerrit.chromium.org/gerrit/4644
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/ap20.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/clock.c | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 75fdf7c22f..6d58914328 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -42,7 +42,7 @@ struct clk_pll_table { }; /* ~0=uninitialized/unknown, 0=false, 1=true */ -int is_tegra2_cold_boot = 0xffffffff; +uint32_t is_tegra2_processor_reset = 0xffffffff; /* * Timing tables for each SOC for all four oscillator options. @@ -387,7 +387,7 @@ void tegra2_start(void) /* FIXME: should have ap20's L2 disabled too? */ - /* Init is_tegra2_cold_boot */ - is_tegra2_cold_boot = check_is_tegra2_cold_boot(); + /* Init is_tegra2_processor_reset */ + is_tegra2_processor_reset = check_is_tegra2_processor_reset(); } diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 0e8acf1d3b..7227e5850a 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -902,7 +902,7 @@ int clock_verify(void) return 0; } -int check_is_tegra2_cold_boot(void) +uint32_t check_is_tegra2_processor_reset(void) { u32 base_reg; struct clk_pll *pll; |