diff options
author | Wolfgang Denk <wd@denx.de> | 2021-09-27 17:42:39 +0200 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2021-09-30 09:08:16 -0400 |
commit | 0cf207ec01cbacae47585fcc26591dd2296507d6 (patch) | |
tree | 573cfefc2ab21a033ae98fa2afbd57f1f6528496 /arch/arm/cpu | |
parent | 0a50b3c97b3408e52589d873d4c7b54ad365a76c (diff) |
WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/arm926ejs/armada100/timer.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fel_utils.S | 20 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 | 36 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 |
4 files changed, 31 insertions, 31 deletions
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c index 6d77ad3b6da..4b96d4aa918 100644 --- a/arch/arm/cpu/arm926ejs/armada100/timer.c +++ b/arch/arm/cpu/arm926ejs/armada100/timer.c @@ -45,7 +45,7 @@ struct armd1tmr_registers { #define TIMER 0 /* Use TIMER 0 */ /* Each timer has 3 match registers */ #define MATCH_CMP(x) ((3 * TIMER) + x) -#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_LOAD_VAL 0xffffffff #define COUNT_RD_REQ 0x1 DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S index 7def44ad1d3..5266515f145 100644 --- a/arch/arm/cpu/armv8/fel_utils.S +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -64,18 +64,18 @@ ENTRY(return_to_fel) /* AArch32 code to restore the state from fel_stash and return back to FEL. */ back_in_32: - .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address - .word 0xe5901008 // ldr r1, [r0, #8] - .word 0xe129f001 // msr CPSR_fc, r1 + .word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address + .word 0xe5901008 // ldr r1, [r0, #8] + .word 0xe129f001 // msr CPSR_fc, r1 .word 0xf57ff06f // isb - .word 0xe590d000 // ldr sp, [r0] - .word 0xe590e004 // ldr lr, [r0, #4] - .word 0xe5901010 // ldr r1, [r0, #16] - .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR - .word 0xe590100c // ldr r1, [r0, #12] - .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR + .word 0xe590d000 // ldr sp, [r0] + .word 0xe590e004 // ldr lr, [r0, #4] + .word 0xe5901010 // ldr r1, [r0, #16] + .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR + .word 0xe590100c // ldr r1, [r0, #12] + .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR .word 0xf57ff06f // isb - .word 0xe12fff1e // bx lr ; return to FEL + .word 0xe12fff1e // bx lr ; return to FEL fel_stash_addr: .word 0x00000000 // receives fel_stash addr, by AA64 code above ENDPROC(return_to_fel) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 6c98d99d0cc..9119d60ffb3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -42,22 +42,22 @@ Flash Layout pre-silicon platforms (simulator and emulator): ------------------------- - | FIT Image | + | FIT Image | | (linux + DTB + RFS) | ------------------------- ----> 0x0120_0000 - | Debug Server FW | + | Debug Server FW | ------------------------- ----> 0x00C0_0000 - | AIOP FW | + | AIOP FW | ------------------------- ----> 0x0070_0000 - | MC FW | + | MC FW | ------------------------- ----> 0x006C_0000 - | MC DPL Blob | + | MC DPL Blob | ------------------------- ----> 0x0020_0000 - | BootLoader + Env| + | BootLoader + Env| ------------------------- ----> 0x0000_1000 - | PBI | + | PBI | ------------------------- ----> 0x0000_0080 - | RCW | + | RCW | ------------------------- ----> 0x0000_0000 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) @@ -70,45 +70,45 @@ Flash Layout ----------------------------------------- ----> 0x5_8790_0000 | | FIT Image (linux + DTB + RFS) (40M) | | ----------------------------------------- ----> 0x5_8510_0000 | - | PHY firmware (2M) | | + | PHY firmware (2M) | | ----------------------------------------- ----> 0x5_84F0_0000 | 64K | Debug Server FW (2M) | | Alt ----------------------------------------- ----> 0x5_84D0_0000 | Bank | AIOP FW (4M) | | ----------------------------------------- ----> 0x5_8490_0000 (vbank4) - | MC DPC Blob (1M) | | + | MC DPC Blob (1M) | | ----------------------------------------- ----> 0x5_8480_0000 | | MC DPL Blob (1M) | | ----------------------------------------- ----> 0x5_8470_0000 | - | MC FW (4M) | | + | MC FW (4M) | | ----------------------------------------- ----> 0x5_8430_0000 | - | BootLoader Environment (1M) | | + | BootLoader Environment (1M) | | ----------------------------------------- ----> 0x5_8420_0000 | | BootLoader (1M) | | ----------------------------------------- ----> 0x5_8410_0000 | - | RCW and PBI (1M) | | + | RCW and PBI (1M) | | ----------------------------------------- ----> 0x5_8400_0000 --- | .. Unused .. (7M) | | ----------------------------------------- ----> 0x5_8390_0000 | | FIT Image (linux + DTB + RFS) (40M) | | ----------------------------------------- ----> 0x5_8110_0000 | - | PHY firmware (2M) | | + | PHY firmware (2M) | | ----------------------------------------- ----> 0x5_80F0_0000 | 64K | Debug Server FW (2M) | | Bank ----------------------------------------- ----> 0x5_80D0_0000 | | AIOP FW (4M) | | ----------------------------------------- ----> 0x5_8090_0000 (vbank0) - | MC DPC Blob (1M) | | + | MC DPC Blob (1M) | | ----------------------------------------- ----> 0x5_8080_0000 | | MC DPL Blob (1M) | | ----------------------------------------- ----> 0x5_8070_0000 | - | MC FW (4M) | | + | MC FW (4M) | | ----------------------------------------- ----> 0x5_8030_0000 | - | BootLoader Environment (1M) | | + | BootLoader Environment (1M) | | ----------------------------------------- ----> 0x5_8020_0000 | | BootLoader (1M) | | ----------------------------------------- ----> 0x5_8010_0000 | - | RCW and PBI (1M) | | + | RCW and PBI (1M) | | ----------------------------------------- ----> 0x5_8000_0000 --- 128-MB NOR flash layout for QDS and RDB boards diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index d8803738f10..3aa1a9c3e5c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -250,7 +250,7 @@ ENTRY(lowlevel_init) * b. We use only Region0 whose NSAID write/read is EN * * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just - * placeholders. + * placeholders. */ .macro tzasc_prog, xreg @@ -259,7 +259,7 @@ ENTRY(lowlevel_init) mov x16, #0x10000 mul x14, \xreg, x16 add x14, x14,x12 - mov x1, #0x8 + mov x1, #0x8 add x1, x1, x14 ldr w0, [x1] /* Filter 0 Gate Keeper Register */ |