diff options
| author | Tom Warren <twarren.nvidia@gmail.com> | 2014-01-24 12:46:16 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-02-03 09:46:46 -0700 |
| commit | 2f5dac9214391efc58dc7ea5267b1322d3b18df6 (patch) | |
| tree | b1f5a0dad86f40897101736f95936ab53b78ad29 /arch/arm/cpu/tegra-common/ap.c | |
| parent | 52ef43b052964c15e051c119641d81e1f7051c14 (diff) | |
ARM: tegra: add common (shared) CPU files
These files are used by both SPL and main U-Boot.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra-common/ap.c')
| -rw-r--r-- | arch/arm/cpu/tegra-common/ap.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index f205be402ab..91d70da6566 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -1,5 +1,5 @@ /* -* (C) Copyright 2010-2011 +* (C) Copyright 2010-2014 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -27,7 +27,7 @@ int tegra_get_chip(void) /* * This is undocumented, Chip ID is bits 15:8 of the register * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for - * Tegra30, and 0x35 for T114. + * Tegra30, 0x35 for T114, and 0x40 for Tegra124. */ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; debug("%s: CHIPID is 0x%02X\n", __func__, rev); @@ -84,7 +84,15 @@ int tegra_get_chip_sku(void) return TEGRA_SOC_T114; } break; + case CHIPID_TEGRA124: + switch (sku_id) { + case SKU_ID_T124_ENG: + default: + return TEGRA_SOC_T124; + } + break; } + /* unknown chip/sku id */ printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", __func__, chip_id, sku_id); @@ -119,8 +127,8 @@ static u32 get_odmdata(void) * ODMDATA is stored in the BCT in IRAM by the BootROM. * The BCT start and size are stored in the BIT in IRAM. * Read the data @ bct_start + (bct_size - 12). This works - * on T20 and T30 BCTs, which are locked down. If this changes - * in new chips (T114, etc.), we can revisit this algorithm. + * on BCTs for currently supported SoCs, which are locked down. + * If this changes in new chips, we can revisit this algorithm. */ u32 bct_start, odmdata; |