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authorTom Rini <trini@ti.com>2014-05-22 14:29:41 -0400
committerTom Rini <trini@ti.com>2014-05-22 14:29:41 -0400
commitf6ed9d50949eb290744bf7606e30763582e2d44b (patch)
tree659cd954a4b4075c7227ea6d1d6ec768b0a2d78a /arch/arm/cpu/sa1100/cpu.c
parent8e3812859670fda61b98458864fa9f014fcd3dcc (diff)
parent05d134b084590684bcf4d832c0035952727b7cd9 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/cpu/sa1100/cpu.c')
-rw-r--r--arch/arm/cpu/sa1100/cpu.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c
index 6651898de23..4c9752a1c82 100644
--- a/arch/arm/cpu/sa1100/cpu.c
+++ b/arch/arm/cpu/sa1100/cpu.c
@@ -17,6 +17,7 @@
#include <common.h>
#include <command.h>
#include <asm/system.h>
+#include <asm/io.h>
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
@@ -52,3 +53,16 @@ static void cache_flush (void)
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}
+
+#define RST_BASE 0x90030000
+#define RSRR 0x00
+#define RCSR 0x04
+
+__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
+{
+ /* repeat endlessly */
+ while (1) {
+ writel(0, RST_BASE + RCSR);
+ writel(1, RST_BASE + RSRR);
+ }
+}