diff options
author | Tom Rini <trini@konsulko.com> | 2017-04-18 11:36:06 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2017-04-18 11:36:06 -0400 |
commit | 3c476d841daa491f87c8f07851038afbdf4d90a8 (patch) | |
tree | 131891877d7b9b112ebc8c05ab88d53b9b18b702 /arch/arm/cpu/armv8 | |
parent | 9481f186d0bb06e492f62144cacdb5a8367e3cd2 (diff) | |
parent | e0dfec863e2ca5088dd797a5b6853d4c0df9002c (diff) |
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu/armv8')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 23 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 26 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/spl.c | 20 |
8 files changed, 65 insertions, 21 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index b24462bede9..12fd80e7dbf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -36,6 +36,7 @@ config ARCH_LS1046A select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A008850 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 @@ -63,6 +64,8 @@ config ARCH_LS2080A select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 + select FSL_TZASC_1 + select FSL_TZASC_2 select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008514 @@ -171,6 +174,20 @@ config SYS_LS_PPA_FW_ADDR QSPI flash, this address is a directly memory-mapped. If it is in a serial accessed flash, such as NAND and SD card, it is a byte offset. + +config SYS_LS_PPA_ESBC_ADDR + hex "hdr address of PPA firmware loading from" + depends on FSL_LS_PPA && CHAIN_OF_TRUST + default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A + default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A + default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A + default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 + help + If the PPA header firmware locate at XIP flash, such as NOR or + QSPI flash, this address is a directly memory-mapped. + If it is in a serial accessed flash, such as NAND and SD + card, it is a byte offset. + endmenu config SYS_FSL_ERRATUM_A010315 @@ -223,6 +240,12 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool +config FSL_TZASC_1 + bool + +config FSL_TZASC_2 + bool + endmenu menu "Layerscape clock tree configuration" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index c9ab93e3d7c..e3ce0184d89 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -22,11 +22,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif -ifneq ($(CONFIG_LS2080A),) +ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif -ifneq ($(CONFIG_LS1043A),) +ifneq ($(CONFIG_ARCH_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d446527616c..c24f3f173c0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -92,7 +92,7 @@ static inline void early_mmu_setup(void) static void fix_pcie_mmu_map(void) { -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A unsigned int i; u32 svr, ver; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -523,7 +523,7 @@ int timer_init(void) #ifdef CONFIG_FSL_LSCH3 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; #endif -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; u32 svr_dev_id; #endif @@ -541,7 +541,7 @@ int timer_init(void) out_le32(cltbenr, 0xf); #endif -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A /* * In certain Layerscape SoCs, the clock for each core's * has an enable bit in the PMU Physical Core Time Base Enable diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 762a95b945c..05c4577753a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -373,8 +373,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif - do_fixup_by_compat_u32(blob, "fixed-clock", - "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", + CONFIG_SYS_CLK_FREQ, 1); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index a2185f2def2..f4273561040 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -76,7 +76,7 @@ ENTRY(lowlevel_init) #ifdef CONFIG_FSL_LSCH3 /* Set Wuo bit for RN-I 20 */ -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A ldr x0, =CCI_AUX_CONTROL_BASE(20) ldr x1, =0x00000010 bl ccn504_set_aux @@ -229,38 +229,40 @@ ENTRY(lowlevel_init) * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just * placeholders. */ +#ifdef CONFIG_FSL_TZASC_1 ldr x1, =TZASC_GATE_KEEPER(0) ldr w0, [x1] /* Filter 0 Gate Keeper Register */ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ str w0, [x1] - ldr x1, =TZASC_GATE_KEEPER(1) - ldr w0, [x1] /* Filter 0 Gate Keeper Register */ - orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ - str w0, [x1] - ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) ldr w0, [x1] /* Region-0 Attributes Register */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ str w0, [x1] + ldr x1, =TZASC_REGION_ID_ACCESS_0(0) + ldr w0, [x1] /* Region-0 Access Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] +#endif +#ifdef CONFIG_FSL_TZASC_2 + ldr x1, =TZASC_GATE_KEEPER(1) + ldr w0, [x1] /* Filter 0 Gate Keeper Register */ + orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ + str w0, [x1] + ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) ldr w0, [x1] /* Region-1 Attributes Register */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ str w0, [x1] - ldr x1, =TZASC_REGION_ID_ACCESS_0(0) - ldr w0, [x1] /* Region-0 Access Register */ - mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ - str w0, [x1] - ldr x1, =TZASC_REGION_ID_ACCESS_0(1) ldr w0, [x1] /* Region-1 Attributes Register */ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ str w0, [x1] - +#endif isb dsb sy #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index ab83e85adcd..4db3c76d729 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -70,6 +70,7 @@ static struct serdes_config serdes2_cfg_tbl[] = { SATA2 } }, {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x51, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, {0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } }, {} }; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index b35ad5fb6f0..7f87bb86897 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -178,7 +178,7 @@ int ppa_init(void) ppa_img_addr = (uintptr_t)ppa_fit_addr; if (fsl_check_boot_mode_secure() != 0) { ret = fsl_secboot_validate(ppa_esbc_hdr, - CONFIG_PPA_KEY_HASH, + PPA_KEY_HASH, &ppa_img_addr); if (ret != 0) printf("PPA validation failed\n"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 73a86807417..eb730e84a46 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -41,13 +41,31 @@ u32 spl_boot_mode(const u32 boot_device) } #ifdef CONFIG_SPL_BUILD + +void spl_board_init(void) +{ +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2) + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif +} + void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); board_early_init_f(); timer_init(); -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A env_init(); #endif get_clocks(); |