diff options
author | Simon Glass <sjg@chromium.org> | 2011-11-29 16:40:10 -0800 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2011-12-01 17:08:10 -0800 |
commit | dbd0840a39a15a950869901dd9668951fd35d01a (patch) | |
tree | 0a1f757ed598e60a911ad35c615caff12b064ead /arch/arm/cpu/armv7 | |
parent | 8d1c7cb54d17a831c8063e27a5187ca30f8d4874 (diff) |
tegra: Move tegra_get_chip_type() to ap20.c
This function is better off in architecture code than board code.
This is quite an invasive change unfortunately.
BUG=chromium-os:23496
TEST=build and boot on Seaboard, T33, Kaen
Change-Id: I17764b134c25b684666d2c0fae2d255ac80e61b1
Reviewed-on: https://gerrit.chromium.org/gerrit/12244
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r-- | arch/arm/cpu/armv7/tegra-common/ap20.c | 43 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/tegra-common/clock.c | 1 |
2 files changed, 39 insertions, 5 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c index 787b3e4b3bc..913d8aaa778 100644 --- a/arch/arm/cpu/armv7/tegra-common/ap20.c +++ b/arch/arm/cpu/armv7/tegra-common/ap20.c @@ -23,18 +23,18 @@ #include <common.h> #include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> +#include <asm/arch-tegra/ap20.h> #include <asm/arch-tegra/bitfield.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/flow.h> -#include <asm/arch/clock.h> +#include <asm/arch-tegra/fuse.h> +#include <asm/arch-tegra/i2c.h> #include <asm/arch-tegra/pmc.h> -#include <asm/arch/pinmux.h> #include <asm/arch-tegra/scu.h> -#include <asm/arch-tegra/i2c.h> #include <asm/arch-tegra/warmboot.h> -#include <asm/arch-tegra/ap20.h> -#include "../../../../../board/nvidia/common/board.h" struct clk_pll_table { u16 n; @@ -94,6 +94,39 @@ enum tegra_family_t { #define GP_HIDREV 0x804 +int tegra_get_chip_type(void) +{ + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; + uint tegra_sku_id; + + tegra_sku_id = readl(&fuse->sku_info) & 0xff; + + switch (tegra_sku_id) { + case SKU_ID_T20: + return TEGRA_SOC_T20; + case SKU_ID_T25SE: + case SKU_ID_AP25: + case SKU_ID_T25: + case SKU_ID_AP25E: + case SKU_ID_T25E: + return TEGRA_SOC_T25; + case SKU_ID_T30: + /* + * T30 has two options. We will return TEGRA_SOC_T30 until + * we have the fdt set up when it may change to + * TEGRA_SOC_T30_408MHZ depending on what we set PLLP to. + */ + if (clock_get_rate(CLOCK_ID_PERIPH) == 408000000) + return TEGRA_SOC_T30_408MHZ; + else + return TEGRA_SOC_T30; + + default: + /* unknown sku id */ + return TEGRA_SOC_UNKNOWN; + } +} + static enum tegra_family_t ap20_get_family(void) { u32 reg, chip_id; diff --git a/arch/arm/cpu/armv7/tegra-common/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c index 65f74fcbc4b..1334df21c77 100644 --- a/arch/arm/cpu/armv7/tegra-common/clock.c +++ b/arch/arm/cpu/armv7/tegra-common/clock.c @@ -1398,4 +1398,5 @@ void clock_init(void) debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); + debug("Chip type = %d\n", tegra_get_chip_type()); } |