Merge branch 'master' of http://git.denx.de/u-boot-sunxi

9 files changed, 585 insertions, 18 deletions

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 33c76ef59d3..dfb0a3e3c09 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -26,13 +26,18 @@ obj-$(CONFIG_MACH_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)	+= clock_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= clock_sun4i.o
+ifdef CONFIG_MACH_SUN8I_A83T
+obj-y				+= clock_sun8i_a83t.o
+else
 obj-$(CONFIG_MACH_SUN8I)	+= clock_sun6i.o
+endif
 obj-$(CONFIG_MACH_SUN9I)	+= clock_sun9i.o
 obj-$(CONFIG_MACH_SUN6I)	+= tzpc.o
 
 obj-$(CONFIG_AXP152_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP209_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP221_POWER)	+= pmic_bus.o
+obj-$(CONFIG_AXP818_POWER)	+= pmic_bus.o
 
 ifndef CONFIG_SPL_BUILD
 ifdef CONFIG_ARMV7_PSCI
@@ -49,6 +54,7 @@ obj-$(CONFIG_MACH_SUN6I)	+= dram_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN8I_A23)	+= dram_sun8i_a23.o
 obj-$(CONFIG_MACH_SUN8I_A33)	+= dram_sun8i_a33.o
+obj-$(CONFIG_MACH_SUN8I_A83T)	+= dram_sun8i_a83t.o
 obj-$(CONFIG_MACH_SUN8I_H3)	+= dram_sun8i_h3.o
 obj-y	+= fel_utils.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 0f26cb00f2b..7dfb7f5340d 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -76,6 +76,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
+	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index 7c8eff959bd..7e6bd6137e9 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -59,7 +59,7 @@ void clock_init_uart(void)
 
 	/* open the clock for uart */
 	setbits_le32(&ccm->apb1_gate,
-		CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
+		CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1));
 }
 
 int clock_twi_onoff(int port, int state)
@@ -67,16 +67,13 @@ int clock_twi_onoff(int port, int state)
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-	if (port > 2)
-		return -1;
-
 	/* set the apb clock gate for twi */
 	if (state)
 		setbits_le32(&ccm->apb1_gate,
-			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
+			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
 	else
 		clrbits_le32(&ccm->apb1_gate,
-			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
+			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 916ee48e4bb..4501884e1c2 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -77,9 +77,6 @@ int clock_twi_onoff(int port, int state)
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-	if (port > 3)
-		return -1;
-
 	/* set the apb clock gate for twi */
 	if (state)
 		setbits_le32(&ccm->apb2_gate,
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c
new file mode 100644
index 00000000000..3e8728fff6c
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c
@@ -0,0 +1,136 @@
+/*
+ * A83 specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	clock_set_pll1(408000000);
+	/* enable pll_hsic, default is 480M */
+	writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg);
+	writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg);
+	while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {}
+
+	/* switch to default 24MHz before changing to hsic */
+	writel(0x0, &ccm->cci400_cfg);
+	sdelay(50);
+	writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg);
+	sdelay(100);
+
+	/* switch before changing pll6 */
+	clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK,
+			AHB1_CLK_SRC_OSC24M);
+	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+	while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {}
+
+	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+	writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset);
+	writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg);
+
+	/* timestamp */
+	writel(1, 0x01720000);
+}
+#endif
+
+void clock_init_uart(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* uart clock source is apb2 */
+	writel(APB2_CLK_SRC_OSC24M|
+	       APB2_CLK_RATE_N_1|
+	       APB2_CLK_RATE_M(1),
+	       &ccm->apb2_div);
+
+	/* open the clock for uart */
+	setbits_le32(&ccm->apb2_gate,
+		     CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
+				       CONFIG_CONS_INDEX - 1));
+
+	/* deassert uart reset */
+	setbits_le32(&ccm->apb2_reset_cfg,
+		     1 << (APB2_RESET_UART_SHIFT +
+			   CONFIG_CONS_INDEX - 1));
+}
+
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	const int p = 0;
+
+	/* Switch to 24MHz clock while changing PLL1 */
+	writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
+		AXI_DIV_2 << AXI1_DIV_SHIFT |
+		CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT |
+		CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+
+	/* clk = 24*n/p, p is ignored if clock is >288MHz */
+	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
+		CCM_PLL1_CTRL_N(clk / 24000000),
+		&ccm->pll1_c0_cfg);
+	while (!(readl(&ccm->pll_stable_status) & 0x01)) {}
+
+	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 |
+		CCM_PLL1_CTRL_N(clk / (24000000)),
+		&ccm->pll1_c1_cfg);
+	while (!(readl(&ccm->pll_stable_status) & 0x02)) {}
+
+	/* Switch CPU to PLL1 */
+	writel(AXI_DIV_2 << AXI0_DIV_SHIFT |
+		AXI_DIV_2 << AXI1_DIV_SHIFT |
+		CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT |
+		CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
+	       &ccm->cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll5(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	unsigned int div1 = 0, div2 = 0;
+
+	/* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */
+	writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+			CCM_PLL5_CTRL_N(clk / (24000000)) |
+			div2 << CCM_PLL5_DIV2_SHIFT |
+			div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);
+
+	udelay(5500);
+}
+
+
+unsigned int clock_get_pll6(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	uint32_t rval = readl(&ccm->pll6_cfg);
+	int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
+	int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+			CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+	int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
+			CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
+	return 24000000 * n / div1 / div2;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index 1e73332d7e6..b9bc70ca86a 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -73,6 +73,8 @@ int print_cpuinfo(void)
 	puts("CPU:   Allwinner H3 (SUN8I)\n");
 #elif defined CONFIG_MACH_SUN9I
 	puts("CPU:   Allwinner A80 (SUN9I)\n");
+#elif defined CONFIG_MACH_SUN8I_A83T
+	puts("CPU:   Allwinner A83T (SUN8I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
 	puts("CPU:   SUNXI Family\n");
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
new file mode 100644
index 00000000000..d757e403dc0
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
@@ -0,0 +1,424 @@
+/*
+ * Sun8i a33 platform dram controller init.
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ *                         Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2015      Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+#define DRAM_CLK_MUL 2
+#define DRAM_CLK_DIV 1
+
+struct dram_para {
+	u8 cs1;
+	u8 seq;
+	u8 bank;
+	u8 rank;
+	u8 rows;
+	u8 bus_width;
+	u16 page_size;
+};
+
+static void mctl_set_cr(struct dram_para *para)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+	writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
+		MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
+		(para->seq ? MCTL_CR_SEQUENCE : 0) |
+		((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
+		MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
+		MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
+		&mctl_com->cr);
+}
+
+static void auto_detect_dram_size(struct dram_para *para)
+{
+	u8 orig_rank = para->rank;
+	int rows, columns;
+
+	/* Row detect */
+	para->page_size = 512;
+	para->seq = 1;
+	para->rows = 16;
+	para->rank = 1;
+	mctl_set_cr(para);
+	for (rows = 11 ; rows < 16 ; rows++) {
+		if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
+			break;
+	}
+
+	/* Column (page size) detect */
+	para->rows = 11;
+	para->page_size = 8192;
+	mctl_set_cr(para);
+	for (columns = 9 ; columns < 13 ; columns++) {
+		if (mctl_mem_matches(1 << columns))
+			break;
+	}
+
+	para->seq = 0;
+	para->rank = orig_rank;
+	para->rows = rows;
+	para->page_size = 1 << columns;
+	mctl_set_cr(para);
+}
+
+static inline int ns_to_t(int nanoseconds)
+{
+	const unsigned int ctrl_freq =
+		CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
+
+	return (ctrl_freq * nanoseconds + 999) / 1000;
+}
+
+static void auto_set_timing_para(struct dram_para *para)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+	u32 reg_val;
+
+	u8 tccd		= 2;
+	u8 tfaw		= ns_to_t(50);
+	u8 trrd		= max(ns_to_t(10), 4);
+	u8 trcd		= ns_to_t(15);
+	u8 trc		= ns_to_t(53);
+	u8 txp		= max(ns_to_t(8), 3);
+	u8 twtr		= max(ns_to_t(8), 4);
+	u8 trtp		= max(ns_to_t(8), 4);
+	u8 twr		= max(ns_to_t(15), 3);
+	u8 trp		= ns_to_t(15);
+	u8 tras		= ns_to_t(38);
+
+	u16 trefi	= ns_to_t(7800) / 32;
+	u16 trfc	= ns_to_t(350);
+
+	/* Fixed timing parameters */
+	u8 tmrw		= 0;
+	u8 tmrd		= 4;
+	u8 tmod		= 12;
+	u8 tcke		= 3;
+	u8 tcksrx	= 5;
+	u8 tcksre	= 5;
+	u8 tckesr	= 4;
+	u8 trasmax	= 24;
+	u8 tcl		= 6; /* CL 12 */
+	u8 tcwl		= 4; /* CWL 8 */
+	u8 t_rdata_en	= 4;
+	u8 wr_latency	= 2;
+
+	u32 tdinit0	= (500 * CONFIG_DRAM_CLK) + 1;		/* 500us */
+	u32 tdinit1	= (360 * CONFIG_DRAM_CLK) / 1000 + 1;	/* 360ns */
+	u32 tdinit2	= (200 * CONFIG_DRAM_CLK) + 1;		/* 200us */
+	u32 tdinit3	= (1 * CONFIG_DRAM_CLK) + 1;		/* 1us */
+
+	u8 twtp		= tcwl + 2 + twr;	/* WL + BL / 2 + tWR */
+	u8 twr2rd	= tcwl + 2 + twtr;	/* WL + BL / 2 + tWTR */
+	u8 trd2wr	= tcl + 2 + 1 - tcwl;	/* RL + BL / 2 + 2 - WL */
+
+	/* Set work mode register */
+	mctl_set_cr(para);
+	/* Set mode register */
+	writel(MCTL_MR0, &mctl_ctl->mr0);
+	writel(MCTL_MR1, &mctl_ctl->mr1);
+	writel(MCTL_MR2, &mctl_ctl->mr2);
+	writel(MCTL_MR3, &mctl_ctl->mr3);
+	/* Set dram timing */
+	reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
+	writel(reg_val, &mctl_ctl->dramtmg0);
+	reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
+	writel(reg_val, &mctl_ctl->dramtmg1);
+	reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
+	writel(reg_val, &mctl_ctl->dramtmg2);
+	reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
+	writel(reg_val, &mctl_ctl->dramtmg3);
+	reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
+	writel(reg_val, &mctl_ctl->dramtmg4);
+	reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
+	writel(reg_val, &mctl_ctl->dramtmg5);
+	/* Set two rank timing and exit self-refresh timing */
+	reg_val = readl(&mctl_ctl->dramtmg8);
+	reg_val &= ~(0xff << 8);
+	reg_val &= ~(0xff << 0);
+	reg_val |= (0x33 << 8);
+	reg_val |= (0x8 << 0);
+	writel(reg_val, &mctl_ctl->dramtmg8);
+	/* Set phy interface time */
+	reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
+			| (wr_latency << 0);
+	/* PHY interface write latency and read latency configure */
+	writel(reg_val, &mctl_ctl->pitmg0);
+	/* Set phy time  PTR0-2 use default */
+	writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
+	writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
+	/* Set refresh timing */
+	reg_val = (trefi << 16) | (trfc << 0);
+	writel(reg_val, &mctl_ctl->rfshtmg);
+}
+
+static void mctl_set_pir(u32 val)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	writel(val, &mctl_ctl->pir);
+	mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
+}
+
+static void mctl_data_train_cfg(struct dram_para *para)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	if (para->rank == 2)
+		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
+	else
+		clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
+}
+
+static int mctl_train_dram(struct dram_para *para)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	mctl_data_train_cfg(para);
+	mctl_set_pir(0x5f3);
+
+	return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
+}
+
+static void set_master_priority(void)
+{
+	writel(0x00a0000d, MCTL_MASTER_CFG0(0));
+	writel(0x00500064, MCTL_MASTER_CFG1(0));
+	writel(0x07000009, MCTL_MASTER_CFG0(1));
+	writel(0x00000600, MCTL_MASTER_CFG1(1));
+	writel(0x01000009, MCTL_MASTER_CFG0(3));
+	writel(0x00000064, MCTL_MASTER_CFG1(3));
+	writel(0x08000009, MCTL_MASTER_CFG0(4));
+	writel(0x00000640, MCTL_MASTER_CFG1(4));
+	writel(0x20000308, MCTL_MASTER_CFG0(8));
+	writel(0x00001000, MCTL_MASTER_CFG1(8));
+	writel(0x02800009, MCTL_MASTER_CFG0(9));
+	writel(0x00000100, MCTL_MASTER_CFG1(9));
+	writel(0x01800009, MCTL_MASTER_CFG0(5));
+	writel(0x00000100, MCTL_MASTER_CFG1(5));
+	writel(0x01800009, MCTL_MASTER_CFG0(7));
+	writel(0x00000100, MCTL_MASTER_CFG1(7));
+	writel(0x00640009, MCTL_MASTER_CFG0(6));
+	writel(0x00000032, MCTL_MASTER_CFG1(6));
+	writel(0x0100000d, MCTL_MASTER_CFG0(2));
+	writel(0x00500080, MCTL_MASTER_CFG1(2));
+}
+
+static int mctl_channel_init(struct dram_para *para)
+{
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+		(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+	struct sunxi_mctl_com_reg * const mctl_com =
+		(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+	u32 low_data_lines_status;  /* Training status of datalines 0 - 7 */
+	u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
+	u32 i, rval;
+
+	auto_set_timing_para(para);
+
+	/* Set dram master access priority */
+	writel(0x000101a0, &mctl_com->bwcr);
+	/* set cpu high priority */
+	writel(0x1, &mctl_com->mapr);
+	set_master_priority();
+	udelay(250);
+
+	/* Disable dram VTC */
+	clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);
+	clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);
+
+	writel(0x94be6fa3, MCTL_PROTECT);
+	udelay(100);
+	clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 26);
+	writel(0x0, MCTL_PROTECT);
+	udelay(100);
+
+
+	/* Set ODT */
+	if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
+		rval = 0x0;
+	else
+		rval = 0x2;
+
+	for (i = 0 ; i < 11 ; i++) {
+		clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16),
+				rval << 24);
+		clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16),
+				rval << 24);
+		clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16),
+				rval << 24);
+		clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16),
+				rval << 24);
+	}
+
+	for (i = 0; i < 31; i++)
+		clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26);
+
+	/* set PLL configuration */
+	if (CONFIG_DRAM_CLK >= 480)
+		setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);
+	else
+		setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);
+
+	/* Auto detect dram config, set 2 rank and 16bit bus-width */
+	para->cs1 = 0;
+	para->rank = 2;
+	para->bus_width = 16;
+	mctl_set_cr(para);
+
+	/* Open DQS gating */
+	clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
+	clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
+
+	if (readl(&mctl_com->cr) & 0x1)
+		writel(0x00000303, &mctl_ctl->odtmap);
+	else
+		writel(0x00000201, &mctl_ctl->odtmap);
+
+	mctl_data_train_cfg(para);
+	/* ZQ calibration */
+	clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
+	clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
+	/* CA calibration */
+	mctl_set_pir(0x0201f3 | 0x1<<10);
+
+	/* DQS gate training */
+	if (mctl_train_dram(para) != 0) {
+		low_data_lines_status  = (readl(DXnGSR0(0)) >> 24) & 0x03;
+		high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
+
+		if (low_data_lines_status == 0x3)
+			return -EIO;
+
+		/* DRAM has only one rank */
+		para->rank = 1;
+		mctl_set_cr(para);
+
+		if (low_data_lines_status == high_data_lines_status)
+			goto done; /* 16 bit bus, 1 rank */
+
+		if (!(low_data_lines_status & high_data_lines_status)) {
+			/* Retry 16 bit bus-width with CS1 set */
+			para->cs1 = 1;
+			mctl_set_cr(para);
+			if (mctl_train_dram(para) == 0)
+				goto done;
+		}
+
+		/* Try 8 bit bus-width */
+		writel(0x0, DXnGCR0(1)); /* Disable high DQ */
+		para->cs1 = 0;
+		para->bus_width = 8;
+		mctl_set_cr(para);
+		if (mctl_train_dram(para) != 0)
+			return -EIO;
+	}
+done:
+	/* Check the dramc status */
+	mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
+
+	/* Close DQS gating */
+	setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
+
+	/* set PGCR3,CKE polarity */
+	writel(0x00aa0060, &mctl_ctl->pgcr3);
+	/* Enable master access */
+	writel(0xffffffff, &mctl_com->maer);
+
+	return 0;
+}
+
+static void mctl_sys_init(struct dram_para *para)
+{
+	struct sunxi_ccm_reg * const ccm =
+			(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
+	clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+	clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+	clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
+
+	clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
+
+	clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
+			CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
+			CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
+	mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << 14);
+	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+	setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+	setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
+
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+	setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+	setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
+
+	/* Set dram master access priority */
+	writel(0x0000e00f, &mctl_ctl->clken);	/* normal */
+
+	udelay(250);
+}
+
+unsigned long sunxi_dram_init(void)
+{
+	struct sunxi_mctl_com_reg * const mctl_com =
+			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+	struct sunxi_mctl_ctl_reg * const mctl_ctl =
+			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+	struct dram_para para = {
+		.cs1 = 0,
+		.bank = 1,
+		.rank = 1,
+		.rows = 15,
+		.bus_width = 16,
+		.page_size = 2048,
+	};
+
+	setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
+
+	writel(0, (SUNXI_PRCM_BASE + 0x1e8));
+	udelay(10);
+
+	mctl_sys_init(&para);
+
+	if (mctl_channel_init(&para) != 0)
+		return 0;
+
+	auto_detect_dram_size(&para);
+
+	/* Enable master software clk */
+	writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
+
+	/* Set DRAM ODT MAP */
+	if (para.rank == 2)
+		writel(0x00000303, &mctl_ctl->odtmap);
+	else
+		writel(0x00000201, &mctl_ctl->odtmap);
+
+	return para.page_size * (para.bus_width / 8) *
+		(1 << (para.bank + para.rank + para.rows));
+}
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c
index b721d6011ae..2020d75fd14 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c
@@ -73,10 +73,10 @@ static void mctl_dq_delay(u32 read, u32 write)
 
 	for (i = 0; i < 4; i++) {
 		val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
-		      DATX_IOCR_READ_DELAY((read >> (i * 4)) & 0xf);
+		      DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
 
 		for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
-			setbits_le32(&mctl_ctl->datx[i].iocr[j], val);
+			writel(val, &mctl_ctl->datx[i].iocr[j]);
 	}
 
 	clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
@@ -85,8 +85,8 @@ static void mctl_dq_delay(u32 read, u32 write)
 		val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
 		      DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
 
-		setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQS], val);
-		setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN], val);
+		writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
+		writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
 	}
 
 	setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
@@ -436,8 +436,8 @@ unsigned long sunxi_dram_init(void)
 			(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 
 	struct dram_para para = {
-		.read_delays = 0x00007979,
-		.write_delays = 0x6aaa0000,
+		.read_delays = 0x00007979,	/* dram_tpr12 */
+		.write_delays = 0x6aaa0000,	/* dram_tpr11 */
 		.dual_rank = 0,
 		.bus_width = 32,
 		.row_bits = 15,
diff --git a/arch/arm/cpu/armv7/sunxi/pmic_bus.c b/arch/arm/cpu/armv7/sunxi/pmic_bus.c
index 9e0512725b4..5b81a8d8e12 100644
--- a/arch/arm/cpu/armv7/sunxi/pmic_bus.c
+++ b/arch/arm/cpu/armv7/sunxi/pmic_bus.c
@@ -23,6 +23,7 @@
 #define AXP221_CTRL_ADDR		0x3e
 #define AXP221_INIT_DATA		0x3e
 
+/* AXP818 device and runtime addresses are same as AXP223 */
 #define AXP223_DEVICE_ADDR		0x3a3
 #define AXP223_RUNTIME_ADDR		0x2d
 
@@ -35,7 +36,7 @@ int pmic_bus_init(void)
 	if (!needs_init)
 		return 0;
 
-#ifdef CONFIG_AXP221_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	p2wi_init();
 	ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -61,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data)
 	return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_read(reg, data);
 # else
@@ -76,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data)
 	return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_write(reg, data);
 # else