diff options
author | Yen Lin <yelin@nvidia.com> | 2011-11-03 19:30:08 -0700 |
---|---|---|
committer | Gerrit <chrome-bot@google.com> | 2011-11-14 11:43:16 -0800 |
commit | f66ac168dc0df9eb7cc4fa1a5334f24d2f168643 (patch) | |
tree | 6f43b515516cb0e7a2a489e63cd6e5bd2568458f /arch/arm/cpu/armv7/tegra-common/ap20.c | |
parent | 9b85a281c8a17d7c9e10ec2c899a26dd1c907072 (diff) |
arm: tegra2: change initial CPU clock to 312Mhz
Set CPU clock initially to 312Mhz; once CPU voltage is
raised, CPU clock will then be raied to 1.2GHz (for T25)
or 1.0GHz (for T20).
BUG=chrome-os-partner:5914
TEST=Build and test on Seaboard
Change-Id: I0c95a1df6b87c896daca8c03c9dc33b245764621
Reviewed-on: https://gerrit.chromium.org/gerrit/11199
Tested-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Doug Anderson <dianders@chromium.org>
Diffstat (limited to 'arch/arm/cpu/armv7/tegra-common/ap20.c')
-rw-r--r-- | arch/arm/cpu/armv7/tegra-common/ap20.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c index a3e7858e634..fb836963c8f 100644 --- a/arch/arm/cpu/armv7/tegra-common/ap20.c +++ b/arch/arm/cpu/armv7/tegra-common/ap20.c @@ -78,6 +78,13 @@ static struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_COUNT] { 0x198, 12, 0, 8}, { 0x198, 26, 0, 8}, }, + + /* TEGRA_SOC2_SLOW: 312 MHz */ + {{ 312, 13, 0, 12}, /* OSC 13M */ + { 260, 16, 0, 8}, /* OSC 19.2M */ + { 312, 12, 0, 12}, /* OSC 12M */ + { 312, 26, 0, 12}, /* OSC 26M */ + }, }; enum tegra_family_t { @@ -147,9 +154,14 @@ void ap20_init_pllx(int slow) /* get chip type. If unknown, assign to T20 */ chip_type = tegra_get_chip_type(); - if (slow || chip_type == TEGRA_SOC_UNKNOWN) + if (chip_type == TEGRA_SOC_UNKNOWN) chip_type = TEGRA_SOC_T20; + /* slow mode only works on T2x now */ + if (slow && ((chip_type == TEGRA_SOC_T20) || + (chip_type == TEGRA_SOC_T25))) + chip_type = TEGRA_SOC2_SLOW; + /* get osc freq */ osc = clock_get_osc_freq(); |