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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2012-08-19 04:40:05 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-10-03 02:04:22 +0200
commit1cdf2482d11f30ad65b64cfcb02c194a5a440f75 (patch)
tree106cd0790030d375a2577ce34bb9470dd671d754 /arch/arm/cpu/armv7/rmobile/lowlevel_init.S
parent4fb44e22ec3ddc48b730865cf2c00e98224cee99 (diff)
arm: rmobile: Add support Renesas SH73A0
Renesas SH73A0 is CPU with Cortex-A9. This supports the basic register definition and GPIO. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch/arm/cpu/armv7/rmobile/lowlevel_init.S')
-rw-r--r--arch/arm/cpu/armv7/rmobile/lowlevel_init.S95
1 files changed, 95 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
new file mode 100644
index 0000000000..2cd410b70f
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+ ldr r0, =MERAM_BASE
+ mov r1, #0x0
+ str r1, [r0]
+
+ mrc p15, 0, r0, c0, c0, 5
+ ands r0, r0, #0xF
+ beq lowlevel_init__
+ b wait_interrupt
+
+ .pool
+ .align 4
+
+wait_interrupt:
+ ldr r1, =ICCICR
+ mov r2, #0x0
+ str r2, [r1]
+ mov r2, #0xF0
+ adds r1, r1, #4 /* ICCPMR */
+ str r2, [r1]
+ ldr r1, =ICCICR
+ mov r2, #0x1
+ str r2, [r1]
+
+wait_loop:
+ wfi
+
+ ldr r2, [r1, #0xC]
+ str r2, [r1, #0x10]
+
+ ldr r0, =MERAM_BASE
+ ldr r2, [r0]
+ cmp r2, #0
+ movne pc, r2
+
+ b wait_loop
+
+wait_loop_end:
+ .pool
+ .align 4
+
+lowlevel_init__:
+
+ mov r0, #0x200000
+
+loop0:
+ subs r0, r0, #1
+ bne loop0
+
+ ldr sp, MERAM_STACK
+
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init
+
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ .pool
+ .align 4
+
+ENDPROC(lowlevel_init)
+ .ltorg
+
+MERAM_STACK:
+ .word LOW_LEVEL_MERAM_STACK