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authorLokesh Vutla <lokeshvutla@ti.com>2013-02-04 04:21:59 +0000
committerTom Rini <trini@ti.com>2013-03-11 11:06:09 -0400
commit9ca8bfea80f38e3b423e339499c861ddc24b830c (patch)
tree5876730eda5da37b21a157f66233dc6d4a3b6757 /arch/arm/cpu/armv7/omap5
parent60e6bdcc948f99e6b24d198c1b9136b0cb4e376b (diff)
ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5')
-rw-r--r--arch/arm/cpu/armv7/omap5/clocks.c3
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c2
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
index eecfbade354..1f3369268da 100644
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -36,6 +36,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
+#include <asm/emif.h>
#ifndef CONFIG_SPL_BUILD
/*
@@ -279,7 +280,7 @@ void scale_vcores(void)
do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
- if (omap_revision() == OMAP5432_ES1_0) {
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
/* Configure LDO SRAM "magic" bits */
writel(2, &prcm->prm_sldo_core_setup);
writel(2, &prcm->prm_sldo_mpu_setup);
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index d0c3ff70218..4def422df1d 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -191,7 +191,7 @@ void do_io_settings(void)
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
- if (omap_revision() <= OMAP5430_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();