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authorLokesh Vutla <lokeshvutla@ti.com>2013-05-30 03:19:38 +0000
committerTom Rini <trini@ti.com>2013-06-10 08:43:10 -0400
commit97405d843ece2a53e67b801e02ee42005d26e172 (patch)
tree13c4b866c44ebbbb7033f7490921fcb6dffa6004 /arch/arm/cpu/armv7/omap5/prcm-regs.c
parent7f36c88f64ee1affd4db78b2c2f4a616abceb84c (diff)
ARM: DRA7xx: clocks: Update PLL values
Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/prcm-regs.c')
-rw-r--r--arch/arm/cpu/armv7/omap5/prcm-regs.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index f3b3155163..b7c2f98ddc 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -951,6 +951,7 @@ struct prcm_regs const dra7xx_prcm = {
/* l4 wkup regs */
.cm_abe_pll_ref_clksel = 0x4ae0610c,
.cm_sys_clksel = 0x4ae06110,
+ .cm_abe_pll_sys_clksel = 0x4ae06118,
.cm_wkup_clkstctrl = 0x4ae07800,
.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,