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authorLokesh Vutla <lokeshvutla@ti.com>2013-02-04 04:21:59 +0000
committerTom Rini <trini@ti.com>2013-03-11 11:06:09 -0400
commit9ca8bfea80f38e3b423e339499c861ddc24b830c (patch)
tree5876730eda5da37b21a157f66233dc6d4a3b6757 /arch/arm/cpu/armv7/omap-common/clocks-common.c
parent60e6bdcc948f99e6b24d198c1b9136b0cb4e376b (diff)
ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap-common/clocks-common.c')
-rw-r--r--arch/arm/cpu/armv7/omap-common/clocks-common.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index b1fd277d6d..1f95fba8cd 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -36,6 +36,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
+#include <asm/emif.h>
#ifndef CONFIG_SPL_BUILD
/*
@@ -299,7 +300,7 @@ static void setup_dplls(void)
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
- if (omap_revision() != OMAP5432_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
DPLL_NO_LOCK, "core");
else