diff options
| author | Peng Fan <Peng.Fan@freescale.com> | 2015-03-14 17:37:55 +0800 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-09 14:41:57 +0100 |
| commit | 3f5248d4ea34f2fc6597abe1eeaa6cce3c0d92de (patch) | |
| tree | 39b8371cd92179a8888e7f39a2a7aab036fa0c8b /arch/arm/cpu/armv7/mx6/clock.c | |
| parent | f0ff9a9f5c3f7b21a37b851e80d819e6de6a1e85 (diff) | |
MLK-10774-3 iMX6SX/SL: Modify SOC to support two ENET
iMX6SX has different enet system clocks with iMX6SL, and has two ENET
controllers. So update clocks and soc APIs accordingly to support this
features.
1. Enet RGMII TX clock source may come from external or internal PLL.
By default, use the external phy CLK_25M output as TX clock source.
When using internal PLL as source, the function enable_fec_anatop_clock
must be called to enable clock for each enet controller.
2. Modify the MAC address function "imx_get_mac_from_fuse" to get either
ENET MAC address.
3. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz
reference clock.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/clock.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 055f44e8e46..74f61bad441 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -485,7 +485,7 @@ void enable_qspi_clk(int qspi_num) #endif #ifdef CONFIG_FEC_MXC -int enable_fec_anatop_clock(enum enet_freq freq) +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) { u32 reg = 0; s32 timeout = 100000; @@ -498,7 +498,14 @@ int enable_fec_anatop_clock(enum enet_freq freq) reg = readl(&anatop->pll_enet); reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; - reg |= freq; + + if (0 == fec_id) { + reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); + } else { + reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); + } if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { @@ -513,8 +520,14 @@ int enable_fec_anatop_clock(enum enet_freq freq) } /* Enable FEC clock */ - reg |= BM_ANADIG_PLL_ENET_ENABLE; + if (0 == fec_id) + reg |= BM_ANADIG_PLL_ENET_ENABLE; + else + reg |= BM_ANADIG_PLL_ENET2_ENABLE; reg &= ~BM_ANADIG_PLL_ENET_BYPASS; +#ifdef CONFIG_FEC_MXC_25M_REF_CLK + reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; +#endif writel(reg, &anatop->pll_enet); #ifdef CONFIG_MX6SX |