diff options
| author | Tom Rini <trini@ti.com> | 2014-10-27 09:05:43 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-27 09:05:43 -0400 |
| commit | 5aa7bece1045c28806ce919099616ebe8fa63325 (patch) | |
| tree | c19240d9c85e3f4f839596e5197c619d872021be /arch/arm/cpu/armv7/keystone/clock.c | |
| parent | 674ca84d11391cd2e7faf8f638fc25ed4b782a91 (diff) | |
| parent | b5ff205cdb0da6eff8a02653bf5192ea8d661faa (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-ti
Diffstat (limited to 'arch/arm/cpu/armv7/keystone/clock.c')
| -rw-r--r-- | arch/arm/cpu/armv7/keystone/clock.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c index 47fc89398d..d13fbc1a4b 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data) tmp &= ~(PLL_BWADJ_HI_MASK); tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK); - /* set PLL Select (bit 13) for PASS PLL */ - if (data->pll == PASS_PLL) - tmp |= PLLCTL_PAPLL; - __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); /* Reset bit: bit 14 for both DDR3 & PASS PLL */ @@ -261,3 +257,16 @@ inline int get_max_arm_speed(void) return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds); } #endif + +void pass_pll_pa_clk_enable(void) +{ + u32 reg; + + reg = readl(keystone_pll_regs[PASS_PLL].reg1); + + reg |= PLLCTL_PAPLL; + writel(reg, keystone_pll_regs[PASS_PLL].reg1); + + /* wait till clock is enabled */ + sdelay(15000); +} |