Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm:
  ARM: Add Calxeda Highbank platform
  dkb: make mmc command as default enabled
  Marvell: dkb: add mmc support
  ARM: pantheon: add mmc definition
  davinci: remove config.mk file from the sources
  ARM:AM33XX: Add support for TI AM335X EVM
  ARM:AM33XX: Added timer support
  ARM:AM33XX: Add emif/ddr support
  ARM:AM33XX: Add clock definitions
  ARM:AM33XX: Added support for AM33xx
  omap3/emif4: fix registers definition
  davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM
  davinci: emac: add support for more than 1 PHYs
  davinci: emac: add new features to autonegotiate for EMAC
  da850evm: Move LPSC configuration to board_early_init_f()
  omap4_panda: Build in cmd_gpio support on panda
  omap: Don't use gpio_free to change direction to input
  mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset
  OMAP3: overo : Add environment variable optargs to bootargs
  OMAP3: overo: Move ethernet CS4 configuration to execute based on board id
  OMAP3: overo : Use ttyO2 instead of ttyS2.
  da830: add support for NAND boot mode
  dm36x: revert cache disable patch
  dm644X: revert cache disable patch
  devkit8000: Add malloc space
  omap: spl: fix build break due to changes in FAT
  OMAP3 SPL: Provide weak omap_rev_string
  omap: beagle: Use ubifs instead of jffs2 for nand boot
  omap: overo: Disable pull-ups on camera PCLK, HS and VS signals
  omap: overo: Configure mux for gpio10
  SPL: Add DMA library
  omap3: Add interface for omap3 DMA
  omap3: Add DMA register accessors
  omap3: Add Base register for DMA
  arm, davinci: add missing LSPC define for MMC/SD1
  U-Boot/SPL: omap4: Make ddr pre-calculated timings as default.
  DaVinci: correct MDSTAT.STATE mask
  omap4: splitting padconfs into common, 4430 and 4460
  omap4: adding revision detection for 4460 ES1.1
  omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL
  gplug: fixed build error as a result of code cleanup patch
  kirkwood_spi: add dummy spi_init()
  gpio: mvmfp: reduce include platform file
  ARM: orion5x: reduce dependence of including platform file
  serial: reduce include platform file for marvell chip
  ARM: kirkwood: reduce dependence of including platform file
  ARM: armada100: reduce dependence of including platform file
  ARM: pantheon: reduce dependence of including platform file
  Armada100: Add env storage support for Marvell gplugD
  Armada100: Add SPI flash support for Marvell gplugD
  Armada100: Add SPI support for Marvell gplugD
  SPI: Add SPI driver support for Marvell Armada100
  dreamplug: initial board support.
  imx: fix coding style
  misc: pmic: drop old Freescale's pmic driver
  MX31: mx31pdk: use new pmic driver
  MX31: mx31ads: use new pmic driver
  MX31: mx31_litekit: use new pmic driver
  MX5: mx53evk: use new pmic driver
  MX5: mx51evk: use new pmic driver
  MX35: mx35pdk: use new pmic driver
  misc: pmic: addI2C  support to pmic_fsl driver
  misc: pmic: use I2C_SET_BUS in pmic I2C
  MX5: efikamx/efikasb: use new pmic driver
  MX3: qong: use new pmic driver
  RTC: Switch mc13783 to generic pmic code
  MX5: vision2: use new pmic driver
  misc: pmic: Freescale PMIC switches to generic PMIC driver
  misc:pmic:samsung Enable PMIC driver at GONI target
  misc:pmic:max8998 MAX8998 support at a new PMIC driver.
  misc:pmic:core New generic PMIC driver
  mx31pdk: Remove unneeded config
  mx31: provide readable WEIM CS accessor
  MX51: vision2: Set global macros
  I2C: Add i2c_get/set_speed() to mxc_i2c.c
  ARM: Update mach-types
  devkit8000: Add config to enable SPL MMC boot
  devkit8000: protect board_mmc_init
  arm, post: add missing post_time_ms for arm
  cosmetic, post: Codingstyle cleanup
  arm, logbuffer: make it compileclean
  tegra2: Enable MMC for Seaboard
  tegra2: Add more pinmux functions
  tegra2: Rename PIN_ to PINGRP_
  tegra2: Add more clock functions
  tegra2: Clean up board code a little
  tegra2: Rename CLOCK_PLL_ID to CLOCK_ID

1 files changed, 201 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
new file mode 100644
index 0000000000..1318365a4a
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -0,0 +1,201 @@
+/*
+ * emif4.c
+ *
+ * AM33XX emif4 configuration file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
+struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
+struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_MAX_RAM_BANK_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+
+#ifdef CONFIG_AM335X_CONFIG_DDR
+static void data_macro_config(int dataMacroNum)
+{
+	struct ddr_data data;
+
+	data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+				|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0));
+	data.datardsratio1 = DDR2_RD_DQS>>2;
+	data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+				|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0));
+	data.datawdsratio1 = DDR2_WR_DQS>>2;
+	data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+				|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0));
+	data.datawiratio1 = DDR2_PHY_WRLVL>>2;
+	data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+				|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0));
+	data.datagiratio1 = DDR2_PHY_GATELVL>>2;
+	data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0));
+	data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2;
+	data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0));
+	data.datawrsratio1 = DDR2_PHY_WR_DATA>>2;
+	data.datadldiff0 = PHY_DLL_LOCK_DIFF;
+
+	config_ddr_data(dataMacroNum, &data);
+}
+
+static void cmd_macro_config(void)
+{
+	struct cmd_control cmd;
+
+	cmd.cmd0csratio = DDR2_RATIO;
+	cmd.cmd0csforce = CMD_FORCE;
+	cmd.cmd0csdelay = CMD_DELAY;
+	cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
+	cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
+
+	cmd.cmd1csratio = DDR2_RATIO;
+	cmd.cmd1csforce = CMD_FORCE;
+	cmd.cmd1csdelay = CMD_DELAY;
+	cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
+	cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
+
+	cmd.cmd2csratio = DDR2_RATIO;
+	cmd.cmd2csforce = CMD_FORCE;
+	cmd.cmd2csdelay = CMD_DELAY;
+	cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
+	cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
+
+	config_cmd_ctrl(&cmd);
+
+}
+
+static void config_vtp(void)
+{
+	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+			&vtpreg->vtp0ctrlreg);
+	writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+			&vtpreg->vtp0ctrlreg);
+	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
+			&vtpreg->vtp0ctrlreg);
+
+	/* Poll for READY */
+	while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
+			VTP_CTRL_READY)
+		;
+}
+
+static void config_emif_ddr2(void)
+{
+	int i;
+	int ret;
+	struct sdram_config cfg;
+	struct sdram_timing tmg;
+	struct ddr_phy_control phyc;
+
+	/*Program EMIF0 CFG Registers*/
+	phyc.reg = EMIF_READ_LATENCY;
+	phyc.reg_sh = EMIF_READ_LATENCY;
+	phyc.reg2 = EMIF_READ_LATENCY;
+
+	tmg.time1 = EMIF_TIM1;
+	tmg.time1_sh = EMIF_TIM1;
+	tmg.time2 = EMIF_TIM2;
+	tmg.time2_sh = EMIF_TIM2;
+	tmg.time3 = EMIF_TIM3;
+	tmg.time3_sh = EMIF_TIM3;
+
+	cfg.sdrcr = EMIF_SDCFG;
+	cfg.sdrcr2 = EMIF_SDCFG;
+	cfg.refresh = 0x00004650;
+	cfg.refresh_sh = 0x00004650;
+
+	/* Program EMIF instance */
+	ret = config_ddr_phy(&phyc);
+	if (ret < 0)
+		printf("Couldn't configure phyc\n");
+
+	ret = config_sdram(&cfg);
+	if (ret < 0)
+		printf("Couldn't configure SDRAM\n");
+
+	ret = set_sdram_timings(&tmg);
+	if (ret < 0)
+		printf("Couldn't configure timings\n");
+
+	/* Delay */
+	for (i = 0; i < 5000; i++)
+		;
+
+	cfg.refresh = EMIF_SDREF;
+	cfg.refresh_sh = EMIF_SDREF;
+	cfg.sdrcr = EMIF_SDCFG;
+	cfg.sdrcr2 = EMIF_SDCFG;
+
+	ret = config_sdram(&cfg);
+	if (ret < 0)
+		printf("Couldn't configure SDRAM\n");
+}
+
+void config_ddr(void)
+{
+	int data_macro_0 = 0;
+	int data_macro_1 = 1;
+	struct ddr_ioctrl ioctrl;
+
+	enable_emif_clocks();
+
+	config_vtp();
+
+	cmd_macro_config();
+
+	data_macro_config(data_macro_0);
+	data_macro_config(data_macro_1);
+
+	writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
+	writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
+
+	ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
+	ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
+	ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
+	ioctrl.data1ctl = DDR_IOCTRL_VALUE;
+	ioctrl.data2ctl = DDR_IOCTRL_VALUE;
+
+	config_io_ctrl(&ioctrl);
+
+	writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
+	writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
+
+	config_emif_ddr2();
+}
+#endif