diff options
| author | Rasmus Villemoes <rasmus.villemoes@prevas.dk> | 2019-09-12 09:17:11 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-01-07 10:26:57 +0100 |
| commit | abaf5c98047338c8d8774ff0a5cbc9efffda92f0 (patch) | |
| tree | 403c65514e691a98c750c0fc85691443f9a70875 /arch/arm/cpu/arm926ejs | |
| parent | fb9462522991a50b95ea00fdbc495634bb6a7cca (diff) | |
arm: mxs: be more careful when enabling gpmi_clk
The data sheet says that the DIV field cannot change while the CLKGATE
bit is set or modified. So do it a little more carefully, by first
clearing the bit, waiting for that to appear, then setting the DIV
field.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Diffstat (limited to 'arch/arm/cpu/arm926ejs')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/mxs.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 585c53baf6..183aa40b6d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -103,8 +103,11 @@ int arch_cpu_init(void) &clkctrl_regs->hw_clkctrl_clkseq_set); /* Set GPMI clock to ref_xtal / 1 */ + clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE); + while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE) + ; clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, - CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); + CLKCTRL_GPMI_DIV_MASK, 1); udelay(1000); |