arm: Remove spear600 boards and the rest of SPEAr support

These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.  As this is
the last of the SPEAr platforms, so remove the rest of the remaining
support as well.

Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

14 files changed, 0 insertions, 1824 deletions

diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile
deleted file mode 100644
index b1b6b4028b..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y	:= cpu.o \
-	   reset.o \
-	   timer.o
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= spl.o
-obj-$(CONFIG_SPEAR600) += spear600.o
-obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
-obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
-obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
-obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
-else
-obj-y += spr_misc.o spr_lowlevel_init.o
-endif
-
-extra-$(CONFIG_SPL_BUILD) := start.o
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
deleted file mode 100644
index 2e0dd9ec33..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_misc.h>
-
-int arch_cpu_init(void)
-{
-	struct misc_regs *const misc_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 periph1_clken, periph_clk_cfg;
-
-	periph1_clken = readl(&misc_p->periph1_clken);
-
-#if defined(CONFIG_SPEAR600)
-	periph1_clken |= MISC_GPT3ENB;
-#endif
-
-#if defined(CONFIG_PL011_SERIAL)
-	periph1_clken |= MISC_UART0ENB;
-
-	periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
-	periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
-	periph_clk_cfg |= CONFIG_SPEAR_UART48M;
-	writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
-#endif
-#if defined(CONFIG_ETH_DESIGNWARE)
-	periph1_clken |= MISC_ETHENB;
-#endif
-#if defined(CONFIG_DW_UDC)
-	periph1_clken |= MISC_USBDENB;
-#endif
-#if defined(CONFIG_SYS_I2C_DW)
-	periph1_clken |= MISC_I2CENB;
-#endif
-#if defined(CONFIG_ST_SMI)
-	periph1_clken |= MISC_SMIENB;
-#endif
-#if defined(CONFIG_NAND_FSMC)
-	periph1_clken |= MISC_FSMCENB;
-#endif
-#if defined(CONFIG_USB_EHCI_SPEAR)
-	periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2;
-#endif
-#if defined(CONFIG_SPEAR_GPIO)
-	periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB;
-#endif
-#if defined(CONFIG_PL022_SPI)
-	periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB;
-#endif
-
-	writel(periph1_clken, &misc_p->periph1_clken);
-
-	return 0;
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
-#if defined(CONFIG_SPEAR600)
-	printf("CPU:   SPEAr600\n");
-#else
-#error CPU not supported in spear platform
-#endif
-	return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
-static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
-			 char *const argv[])
-{
-	if (argc != 2)
-		goto usage;
-
-	if (strncmp(argv[1], "hw", 2) == 0) {
-		/* 1-bit HW ECC */
-		printf("Switching to 1-bit HW ECC\n");
-		fsmc_nand_switch_ecc(1);
-	} else if (strncmp(argv[1], "bch4", 2) == 0) {
-		/* 4-bit SW ECC BCH4 */
-		printf("Switching to 4-bit SW ECC (BCH4)\n");
-		fsmc_nand_switch_ecc(4);
-	} else {
-		goto usage;
-	}
-
-	return 0;
-
-usage:
-	printf("Usage: nandecc %s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(
-	nandecc, 2, 0,	do_switch_ecc,
-	"switch NAND ECC calculation algorithm",
-	"hw|bch4 - Switch between NAND hardware 1-bit HW and"
-	" 4-bit SW BCH\n"
-);
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/reset.c b/arch/arm/cpu/arm926ejs/spear/reset.c
deleted file mode 100644
index 97a624e16c..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/reset.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_syscntl.h>
-#include <linux/delay.h>
-
-void reset_cpu(void)
-{
-	struct syscntl_regs *syscntl_regs_p =
-	    (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
-
-	printf("System is going to reboot ...\n");
-
-	/*
-	 * This 1 second delay will allow the above message
-	 * to be printed before reset
-	 */
-	udelay((1000 * 1000));
-
-	/* Going into slow mode before resetting SOC */
-	writel(0x02, &syscntl_regs_p->scctrl);
-
-	/*
-	 * Writing any value to the system status register will
-	 * reset the SoC
-	 */
-	writel(0x00, &syscntl_regs_p->scsysstat);
-
-	/* system will restart */
-	while (1)
-		;
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c
deleted file mode 100644
index b31ede5eb9..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ /dev/null
@@ -1,223 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_defs.h>
-
-void spear_late_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	writel(0x80000007, &misc_p->arb_icm_ml1);
-	writel(0x80000007, &misc_p->arb_icm_ml2);
-	writel(0x80000007, &misc_p->arb_icm_ml3);
-	writel(0x80000007, &misc_p->arb_icm_ml4);
-	writel(0x80000007, &misc_p->arb_icm_ml5);
-	writel(0x80000007, &misc_p->arb_icm_ml6);
-	writel(0x80000007, &misc_p->arb_icm_ml7);
-	writel(0x80000007, &misc_p->arb_icm_ml8);
-	writel(0x80000007, &misc_p->arb_icm_ml9);
-}
-
-static void sel_1v8(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 ddr1v8, ddr2v5;
-
-	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
-	ddr2v5 &= 0x8080ffc0;
-	ddr2v5 |= 0x78000003;
-	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
-
-	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
-	ddr1v8 &= 0x8080ffc0;
-	ddr1v8 |= 0x78000010;
-	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
-
-	while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
-		;
-}
-
-static void sel_2v5(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 ddr1v8, ddr2v5;
-
-	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
-	ddr1v8 &= 0x8080ffc0;
-	ddr1v8 |= 0x78000003;
-	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
-
-	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
-	ddr2v5 &= 0x8080ffc0;
-	ddr2v5 |= 0x78000010;
-	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
-
-	while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
-		;
-}
-
-/*
- * plat_ddr_init:
- */
-void plat_ddr_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 ddrpad;
-	u32 core3v3, ddr1v8, ddr2v5;
-
-	/* DDR pad register configurations */
-	ddrpad = readl(&misc_p->ddr_pad);
-	ddrpad &= ~DDR_PAD_CNF_MSK;
-
-#if (CONFIG_DDR_HCLK)
-	ddrpad |= 0xEAAB;
-#elif (CONFIG_DDR_2HCLK)
-	ddrpad |= 0xEAAD;
-#elif (CONFIG_DDR_PLL2)
-	ddrpad |= 0xEAAD;
-#endif
-	writel(ddrpad, &misc_p->ddr_pad);
-
-	/* Compensation register configurations */
-	core3v3 = readl(&misc_p->core_3v3_compensation);
-	core3v3 &= 0x8080ffe0;
-	core3v3 |= 0x78000002;
-	writel(core3v3, &misc_p->core_3v3_compensation);
-
-	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
-	ddr1v8 &= 0x8080ffc0;
-	ddr1v8 |= 0x78000004;
-	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
-
-	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
-	ddr2v5 &= 0x8080ffc0;
-	ddr2v5 |= 0x78000004;
-	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
-
-	if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
-		/* Software memory configuration */
-		if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
-			sel_1v8();
-		else
-			sel_2v5();
-	} else {
-		/* Hardware memory configuration */
-		if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
-			sel_1v8();
-		else
-			sel_2v5();
-	}
-}
-
-/*
- * xxx_boot_selected:
- *
- * return true if the particular booting option is selected
- * return false otherwise
- */
-static u32 read_bootstrap(void)
-{
-	return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
-		& CONFIG_SPEAR_BOOTSTRAPMASK;
-}
-
-int snor_boot_selected(void)
-{
-	u32 bootstrap = read_bootstrap();
-
-	if (SNOR_BOOT_SUPPORTED) {
-		/* Check whether SNOR boot is selected */
-		if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
-			CONFIG_SPEAR_ONLYSNORBOOT)
-			return true;
-
-		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
-			CONFIG_SPEAR_NORNAND8BOOT)
-			return true;
-
-		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
-			CONFIG_SPEAR_NORNAND16BOOT)
-			return true;
-	}
-
-	return false;
-}
-
-int nand_boot_selected(void)
-{
-	u32 bootstrap = read_bootstrap();
-
-	if (NAND_BOOT_SUPPORTED) {
-		/* Check whether NAND boot is selected */
-		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
-			CONFIG_SPEAR_NORNAND8BOOT)
-			return true;
-
-		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
-			CONFIG_SPEAR_NORNAND16BOOT)
-			return true;
-	}
-
-	return false;
-}
-
-int pnor_boot_selected(void)
-{
-	/* Parallel NOR boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int usb_boot_selected(void)
-{
-	u32 bootstrap = read_bootstrap();
-
-	if (USB_BOOT_SUPPORTED) {
-		/* Check whether USB boot is selected */
-		if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
-			return true;
-	}
-
-	return false;
-}
-
-int tftp_boot_selected(void)
-{
-	/* TFTP boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int uart_boot_selected(void)
-{
-	/* UART boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int spi_boot_selected(void)
-{
-	/* SPI boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int i2c_boot_selected(void)
-{
-	/* I2C boot is not selected in any SPEAr600 revision */
-	return false;
-}
-
-int mmc_boot_selected(void)
-{
-	return false;
-}
-
-void plat_late_init(void)
-{
-	spear_late_init();
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
deleted file mode 100644
index 693cee1ab3..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ /dev/null
@@ -1,296 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <init.h>
-#include <spl.h>
-#include <version.h>
-#include <asm/io.h>
-#include <asm/ptrace.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_syscntl.h>
-#include <linux/mtd/st_smi.h>
-
-/* Reserve some space to store the BootROM's stack pointer during SPL operation.
- * The BSS cannot be used for this purpose because it will be zeroed after
- * having stored the pointer, so force the location to the data section.
- */
-u32 bootrom_stash_sp __section(".data");
-
-static void ddr_clock_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 clkenb, ddrpll;
-
-	clkenb = readl(&misc_p->periph1_clken);
-	clkenb &= ~PERIPH_MPMCMSK;
-	clkenb |= PERIPH_MPMC_WE;
-
-	/* Intentionally done twice */
-	writel(clkenb, &misc_p->periph1_clken);
-	writel(clkenb, &misc_p->periph1_clken);
-
-	ddrpll = readl(&misc_p->pll_ctr_reg);
-	ddrpll &= ~MEM_CLK_SEL_MSK;
-#if (CONFIG_DDR_HCLK)
-	ddrpll |= MEM_CLK_HCLK;
-#elif (CONFIG_DDR_2HCLK)
-	ddrpll |= MEM_CLK_2HCLK;
-#elif (CONFIG_DDR_PLL2)
-	ddrpll |= MEM_CLK_PLL2;
-#else
-#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
-#endif
-	writel(ddrpll, &misc_p->pll_ctr_reg);
-
-	writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
-			&misc_p->periph1_clken);
-}
-
-static void mpmc_init_values(void)
-{
-	u32 i;
-	u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
-	u32 *mpmc_val_p = &mpmc_conf_vals[0];
-
-	for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
-		writel(*mpmc_val_p, mpmc_reg_p);
-
-	mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
-
-	/*
-	 * MPMC controller start
-	 * MPMC waiting for DLLLOCKREG high
-	 */
-	writel(0x01000100, &mpmc_reg_p[7]);
-
-	while (!(readl(&mpmc_reg_p[3]) & 0x10000))
-		;
-}
-
-static void mpmc_init(void)
-{
-	/* Clock related settings for DDR */
-	ddr_clock_init();
-
-	/*
-	 * DDR pad register bits are different for different SoCs
-	 * Compensation values are also handled separately
-	 */
-	plat_ddr_init();
-
-	/* Initialize mpmc register values */
-	mpmc_init_values();
-}
-
-static void pll_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	/* Initialize PLLs */
-	writel(FREQ_332, &misc_p->pll1_frq);
-	writel(0x1C0A, &misc_p->pll1_cntl);
-	writel(0x1C0E, &misc_p->pll1_cntl);
-	writel(0x1C06, &misc_p->pll1_cntl);
-	writel(0x1C0E, &misc_p->pll1_cntl);
-
-	writel(FREQ_332, &misc_p->pll2_frq);
-	writel(0x1C0A, &misc_p->pll2_cntl);
-	writel(0x1C0E, &misc_p->pll2_cntl);
-	writel(0x1C06, &misc_p->pll2_cntl);
-	writel(0x1C0E, &misc_p->pll2_cntl);
-
-	/* wait for pll locks */
-	while (!(readl(&misc_p->pll1_cntl) & 0x1))
-		;
-	while (!(readl(&misc_p->pll2_cntl) & 0x1))
-		;
-}
-
-static void mac_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
-			&misc_p->periph1_clken);
-
-	writel(SYNTH23, &misc_p->gmac_synth_clk);
-
-	switch (get_socrev()) {
-	case SOC_SPEAR600_AA:
-	case SOC_SPEAR600_AB:
-	case SOC_SPEAR600_BA:
-	case SOC_SPEAR600_BB:
-	case SOC_SPEAR600_BC:
-	case SOC_SPEAR600_BD:
-		writel(0x0, &misc_p->gmac_ctr_reg);
-		break;
-
-	case SOC_SPEAR300:
-	case SOC_SPEAR310:
-	case SOC_SPEAR320:
-		writel(0x4, &misc_p->gmac_ctr_reg);
-		break;
-	}
-
-	writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
-			&misc_p->periph1_clken);
-
-	writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
-			&misc_p->periph1_rst);
-	writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
-			&misc_p->periph1_rst);
-}
-
-static void sys_init(void)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct syscntl_regs *syscntl_p =
-		(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
-
-	/* Set system state to SLOW */
-	writel(SLOW, &syscntl_p->scctrl);
-	writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
-
-	/* Initialize PLLs */
-	pll_init();
-
-	/*
-	 * Ethernet configuration
-	 * To be done only if the tftp boot is not selected already
-	 * Boot code ensures the correct configuration in tftp booting
-	 */
-	if (!tftp_boot_selected())
-		mac_init();
-
-	writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
-	writel(0x555, &misc_p->amba_clk_cfg);
-
-	writel(NORMAL, &syscntl_p->scctrl);
-
-	/* Wait for system to switch to normal mode */
-	while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
-		!= NORMAL)
-		;
-}
-
-/*
- * get_socrev
- *
- * Get SoC Revision.
- * @return SOC_SPEARXXX
- */
-int get_socrev(void)
-{
-#if defined(CONFIG_SPEAR600)
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	u32 soc_id = readl(&misc_p->soc_core_id);
-	u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
-	u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
-
-	if ((pri_socid == 'B') && (sec_socid == 'B'))
-		return SOC_SPEAR600_BB;
-	else if ((pri_socid == 'B') && (sec_socid == 'C'))
-		return SOC_SPEAR600_BC;
-	else if ((pri_socid == 'B') && (sec_socid == 'D'))
-		return SOC_SPEAR600_BD;
-	else if (soc_id == 0)
-		return SOC_SPEAR600_BA;
-	else
-		return SOC_SPEAR_NA;
-#endif
-}
-
-/*
- * SNOR (Serial NOR flash) related functions
- */
-static void snor_init(void)
-{
-	struct smi_regs *const smicntl =
-		(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
-
-	/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
-	writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
-	       &smicntl->smi_cr1);
-}
-
-u32 spl_boot_device(void)
-{
-	u32 mode = 0;
-
-	if (usb_boot_selected()) {
-		mode = BOOT_DEVICE_BOOTROM;
-	} else if (snor_boot_selected()) {
-		/* SNOR-SMI initialization */
-		snor_init();
-
-		mode = BOOT_DEVICE_NOR;
-	}
-
-	return mode;
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	spl_boot_list[0] = spl_boot_device();
-
-	/*
-	 * If the main boot device (eg. NOR) is empty, try to jump back into the
-	 * BootROM for USB boot process.
-	 */
-	if (USB_BOOT_SUPPORTED)
-		spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
-}
-
-void board_init_f(ulong dummy)
-{
-	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	/* Initialize PLLs */
-	sys_init();
-
-	preloader_console_init();
-	arch_cpu_init();
-
-	/* Enable IPs (release reset) */
-	writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
-
-	/* Initialize MPMC */
-	puts("Configure DDR\n");
-	mpmc_init();
-	spear_late_init();
-}
-
-/*
- * In a few cases (Ethernet, UART or USB boot, we might want to go back into the
- * BootROM code right after having initialized a few components like the DRAM).
- * The following function is called from SPL common code (board_init_r).
- */
-int board_return_to_bootrom(struct spl_image_info *spl_image,
-			    struct spl_boot_device *bootdev)
-{
-	/*
-	 * Retrieve the BootROM's stack pointer and jump back to the start of
-	 * the SPL, where we can easily branch back into the BootROM. Don't do
-	 * it right here because SPL might be compiled in Thumb mode while the
-	 * BootROM expects ARM mode.
-	 */
-	asm volatile ("ldr r0, =bootrom_stash_sp;"
-		      "ldr r0, [r0];"
-		      "mov sp, r0;"
-#if defined(CONFIG_SPL_SYS_THUMB_BUILD)
-		      "blx back_to_bootrom;"
-#else
-		      "bl back_to_bootrom;"
-#endif
-		      );
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
deleted file mode 100644
index 79ab2a70dc..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-
-#if (CONFIG_DDR_PLL2)
-
-const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-	0x00000001,
-	0x00000000,
-	0x01000000,
-	0x00000101,
-	0x00000001,
-	0x01000000,
-	0x00010001,
-	0x00000100,
-	0x00010001,
-	0x00000003,
-	0x01000201,
-	0x06000202,
-	0x06060106,
-	0x03050502,
-	0x03040404,
-	0x02020503,
-	0x02010106,
-	0x03000404,
-	0x02030202,
-	0x03000204,
-	0x0707073f,
-	0x07070707,
-	0x06060607,
-	0x06060606,
-	0x05050506,
-	0x05050505,
-	0x04040405,
-	0x04040404,
-	0x03030304,
-	0x03030303,
-	0x02020203,
-	0x02020202,
-	0x01010102,
-	0x01010101,
-	0x08080a01,
-	0x0000023f,
-	0x00040800,
-	0x00000000,
-	0x00000f02,
-	0x00001b1b,
-	0x7f000000,
-	0x005f0000,
-	0x1c040b6a,
-	0x00640064,
-	0x00640064,
-	0x00640064,
-	0x00000064,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x000007ff,
-	0x00000000,
-	0x47ec00c8,
-	0x00c8001f,
-	0x00000000,
-	0x0000cd98,
-	0x00000000,
-	0x03030100,
-	0x03030303,
-	0x03030303,
-	0x03030303,
-	0x00270000,
-	0x00250027,
-	0x00300000,
-	0x008900b7,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
deleted file mode 100644
index 121b636077..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-
-#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
-
-const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-#if (CONFIG_DDR_PLL2)
-	0x00000001,
-	0x00000000,
-#elif (CONFIG_DDR_2HCLK)
-	0x02020201,
-	0x02020202,
-#endif
-	0x01000000,
-	0x00000101,
-	0x00000101,
-	0x01000000,
-	0x00010001,
-	0x00000100,
-	0x01010001,
-	0x00000201,
-	0x01000101,
-	0x06000002,
-	0x06060106,
-	0x03050502,
-	0x03040404,
-	0x02020503,
-	0x02010106,
-	0x03000405,
-	0x03040202,
-	0x04000305,
-	0x0707073f,
-	0x07070707,
-	0x06060607,
-	0x06060606,
-	0x05050506,
-	0x05050505,
-	0x04040405,
-	0x04040404,
-	0x03030304,
-	0x03030303,
-	0x02020203,
-	0x02020202,
-	0x01010102,
-	0x01010101,
-	0x0a0a0a01,
-	0x0000023f,
-	0x00050a00,
-	0x11000000,
-	0x00001302,
-	0x00000A0A,
-	0x72000000,
-	0x00550000,
-	0x2b050e86,
-	0x00640064,
-	0x00640064,
-	0x00640064,
-	0x00000064,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00000a24,
-	0x43C20000,
-	0x5b1c00c8,
-	0x00c8002e,
-	0x00000000,
-	0x0001046b,
-	0x00000000,
-	0x03030100,
-	0x03030303,
-	0x03030303,
-	0x03030303,
-	0x00210000,
-	0x00010021,
-	0x00200000,
-	0x006c0090,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
deleted file mode 100644
index 64c8bab9bf..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-
-#if (CONFIG_DDR_HCLK)
-
-const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-	0x03030301,
-	0x03030303,
-	0x01000000,
-	0x00000101,
-	0x00000001,
-	0x01000000,
-	0x00010001,
-	0x00000100,
-	0x00010001,
-	0x00000003,
-	0x01000201,
-	0x06000202,
-	0x06060106,
-	0x03050502,
-	0x03040404,
-	0x02020503,
-	0x02010106,
-	0x03000404,
-	0x02020202,
-	0x03000203,
-	0x0707073f,
-	0x07070707,
-	0x06060607,
-	0x06060606,
-	0x05050506,
-	0x05050505,
-	0x04040405,
-	0x04040404,
-	0x03030304,
-	0x03030303,
-	0x02020203,
-	0x02020202,
-	0x01010102,
-	0x01010101,
-	0x08080a01,
-	0x0000023f,
-	0x00030600,
-	0x00000000,
-	0x00000a02,
-	0x00001c1c,
-	0x7f000000,
-	0x005f0000,
-	0x12030743,
-	0x00640064,
-	0x00640064,
-	0x00640064,
-	0x00000064,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x0000050e,
-	0x00000000,
-	0x2d8900c8,
-	0x00c80014,
-	0x00000000,
-	0x00008236,
-	0x00000000,
-	0x03030100,
-	0x03030303,
-	0x03030303,
-	0x03030303,
-	0x00400000,
-	0x003a0040,
-	0x00680000,
-	0x00d80120,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
deleted file mode 100644
index 87654663fc..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2009
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
- */
-
-#include <common.h>
-
-#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
-
-const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
-#if (CONFIG_DDR_PLL2)
-	0x00000001,
-	0x00000000,
-#elif (CONFIG_DDR_2HCLK)
-	0x02020201,
-	0x02020202,
-#endif
-	0x01000000,
-	0x00000101,
-	0x00000101,
-	0x01000000,
-	0x00010001,
-	0x00000100,
-	0x01010001,
-	0x00000201,
-	0x01000101,
-	0x06000002,
-	0x06060106,
-	0x03050502,
-	0x03040404,
-	0x02020503,
-#ifdef CONFIG_X600
-	0x02030206,
-#else
-	0x02010106,
-#endif
-	0x03000405,
-	0x03040202,
-	0x04000305,
-	0x0707073f,
-	0x07070707,
-	0x06060607,
-	0x06060606,
-	0x05050506,
-	0x05050505,
-	0x04040405,
-	0x04040404,
-	0x03030304,
-	0x03030303,
-	0x02020203,
-	0x02020202,
-	0x01010102,
-	0x01010101,
-	0x0a0a0a01,
-	0x0000023f,
-	0x00050a00,
-	0x11000000,
-	0x00001302,
-	0x00000A0A,
-#ifdef CONFIG_X600
-	0x7f000000,
-	0x005c0000,
-#else
-	0x72000000,
-	0x00550000,
-#endif
-	0x2b050e86,
-	0x00640064,
-	0x00640064,
-	0x00640064,
-	0x00000064,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00200020,
-	0x00000a24,
-	0x43C20000,
-	0x5b1c00c8,
-	0x00c8002e,
-	0x00000000,
-	0x0001046b,
-	0x00000000,
-	0x03030100,
-	0x03030303,
-	0x03030303,
-	0x03030303,
-	0x00210000,
-	0x00010021,
-	0x00200000,
-	0x006c0090,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x003fffff,
-	0x003fffff,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
deleted file mode 100644
index 417e87a7b5..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
+++ /dev/null
@@ -1,173 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <config.h>
-
-/*
- * platform specific initializations are already done in Xloader
- * Initializations already done include
- * DDR, PLLs, IP's clock enable and reset release etc
- */
-.globl lowlevel_init
-lowlevel_init:
-	mov	pc, lr
-
-/* void setfreq(unsigned int device, unsigned int frequency) */
-.global setfreq
-setfreq:
-	stmfd 	sp!,{r14}
-	stmfd 	sp!,{r0-r12}
-
-	mov  	r8,sp
-	ldr 	sp,SRAM_STACK_V
-
-	/* Saving the function arguements for later use */
-	mov  	r4,r0
-	mov  	r5,r1
-
-	/* Putting DDR into self refresh */
-	ldr 	r0,DDR_07_V
-	ldr	r1,[r0]
-	ldr	r2,DDR_ACTIVE_V
-	bic	r1, r1, r2
-	str	r1,[r0]
-	ldr 	r0,DDR_57_V
-	ldr	r1,[r0]
-	ldr	r2,CYCLES_MASK_V
-	bic	r1, r1, r2
-	ldr	r2,REFRESH_CYCLES_V
-	orr	r1, r1, r2, lsl #16
-	str	r1,[r0]
-	ldr 	r0,DDR_07_V
-	ldr	r1,[r0]
-	ldr	r2,SREFRESH_MASK_V
-	orr	r1, r1, r2
-	str	r1,[r0]
-
-	/* flush pipeline */
-	b	flush
-	.align 5
-flush:
-	/* Delay to ensure self refresh mode */
-	ldr	r0,SREFRESH_DELAY_V
-delay:
-	sub	r0,r0,#1
-	cmp	r0,#0
-	bne	delay
-
-	/* Putting system in slow mode */
-	ldr	r0,SCCTRL_V
-	mov	r1,#2
-	str	r1,[r0]
-
-	/* Changing PLL(1/2) frequency */
-	mov	r0,r4
-	mov	r1,r5
-
-	cmp	r4,#0
-	beq	pll1_freq
-
-	/* Change PLL2 (DDR frequency) */
-	ldr	r6,PLL2_FREQ_V
-	ldr	r7,PLL2_CNTL_V
-	b	pll2_freq
-
-pll1_freq:
-	/* Change PLL1 (CPU frequency) */
-	ldr	r6,PLL1_FREQ_V
-	ldr	r7,PLL1_CNTL_V
-
-pll2_freq:
-	mov	r0,r6
-	ldr	r1,[r0]
-	ldr	r2,PLLFREQ_MASK_V
-	bic	r1,r1,r2
-	mov	r2,r5,lsr#1
-	orr	r1,r1,r2,lsl#24
-	str	r1,[r0]
-
-	mov	r0,r7
-	ldr	r1,P1C0A_V
-	str	r1,[r0]
-	ldr	r1,P1C0E_V
-	str	r1,[r0]
-	ldr	r1,P1C06_V
-	str	r1,[r0]
-	ldr	r1,P1C0E_V
-	str	r1,[r0]
-
-lock:
-	ldr	r1,[r0]
-	and	r1,r1,#1
-	cmp	r1,#0
-	beq	lock
-
-	/* Putting system back to normal mode */
-	ldr	r0,SCCTRL_V
-	mov	r1,#4
-	str	r1,[r0]
-
-	/* Putting DDR back to normal */
-	ldr	r0,DDR_07_V
-	ldr	r1,[R0]
-	ldr	r2,SREFRESH_MASK_V
-	bic	r1, r1, r2
-	str	r1,[r0]
-	ldr	r2,DDR_ACTIVE_V
-	orr	r1, r1, r2
-	str	r1,[r0]
-
-	/* Delay to ensure self refresh mode */
-	ldr	r0,SREFRESH_DELAY_V
-1:
-	sub	r0,r0,#1
-	cmp	r0,#0
-	bne	1b
-
-	mov	sp,r8
-	/* Resuming back to code */
-	ldmia	sp!,{r0-r12}
-	ldmia	sp!,{pc}
-
-SCCTRL_V:
-	.word 0xfca00000
-PLL1_FREQ_V:
-	.word 0xfca8000C
-PLL1_CNTL_V:
-	.word 0xfca80008
-PLL2_FREQ_V:
-	.word 0xfca80018
-PLL2_CNTL_V:
-	.word 0xfca80014
-PLLFREQ_MASK_V:
-	.word 0xff000000
-P1C0A_V:
-	.word 0x1C0A
-P1C0E_V:
-	.word 0x1C0E
-P1C06_V:
-	.word 0x1C06
-
-SREFRESH_DELAY_V:
-	.word 0x9999
-SRAM_STACK_V:
-	.word 0xD2800600
-DDR_07_V:
-	.word 0xfc60001c
-DDR_ACTIVE_V:
-	.word 0x01000000
-DDR_57_V:
-	.word 0xfc6000e4
-CYCLES_MASK_V:
-	.word 0xffff0000
-REFRESH_CYCLES_V:
-	.word 0xf0f0
-SREFRESH_MASK_V:
-	.word 0x00010000
-
-.global setfreq_sz
-setfreq_sz:
-	.word setfreq_sz - setfreq
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_misc.c b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
deleted file mode 100644
index 044052b32f..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/spr_misc.c
+++ /dev/null
@@ -1,253 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <command.h>
-#include <cpu_func.h>
-#include <env.h>
-#include <i2c.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <linux/mtd/st_smi.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_emi.h>
-#include <asm/arch/spr_defs.h>
-
-#define CPU		0
-#define DDR		1
-#define SRAM_REL	0xD2801000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer);
-#endif
-
-int dram_init(void)
-{
-	/* Store complete RAM size and return */
-	gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
-
-	return 0;
-}
-
-int dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = gd->ram_size;
-
-	return 0;
-}
-
-int board_early_init_f()
-{
-#if defined(CONFIG_ST_SMI)
-	smi_init();
-#endif
-	return 0;
-}
-int misc_init_r(void)
-{
-#if defined(CONFIG_CMD_NET)
-	uchar mac_id[6];
-
-	if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
-		eth_env_set_enetaddr("ethaddr", mac_id);
-#endif
-	env_set("verify", "n");
-
-#if defined(CONFIG_SPEAR_USBTTY)
-	env_set("stdin", "usbtty");
-	env_set("stdout", "usbtty");
-	env_set("stderr", "usbtty");
-
-#ifndef CONFIG_SYS_NO_DCACHE
-	dcache_enable();
-#endif
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_SPEAR_EMI
-struct cust_emi_para {
-	unsigned int tap;
-	unsigned int tsdp;
-	unsigned int tdpw;
-	unsigned int tdpr;
-	unsigned int tdcs;
-};
-
-/* EMI timing setting of m28w640hc of linux kernel */
-const struct cust_emi_para emi_timing_m28w640hc = {
-	.tap = 0x10,
-	.tsdp = 0x05,
-	.tdpw = 0x0a,
-	.tdpr = 0x0a,
-	.tdcs = 0x05,
-};
-
-/* EMI timing setting of bootrom */
-const struct cust_emi_para emi_timing_bootrom = {
-	.tap = 0xf,
-	.tsdp = 0x0,
-	.tdpw = 0xff,
-	.tdpr = 0x111,
-	.tdcs = 0x02,
-};
-
-void spear_emi_init(void)
-{
-	const struct cust_emi_para *p = &emi_timing_m28w640hc;
-	struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
-	unsigned int cs;
-	unsigned int val, tmp;
-
-	val = readl(CONFIG_SPEAR_RASBASE);
-
-	if (val & EMI_ACKMSK)
-		tmp = 0x3f;
-	else
-		tmp = 0x0;
-
-	writel(tmp, &emi_regs_p->ack);
-
-	for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
-		writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
-		writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
-		writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
-		writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
-		writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
-		writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
-		       &emi_regs_p->bank_regs[cs].control);
-	}
-}
-#endif
-
-int spear_board_init(ulong mach_type)
-{
-	gd->bd->bi_arch_number = mach_type;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
-
-#ifdef CONFIG_SPEAR_EMI
-	spear_emi_init();
-#endif
-	return 0;
-}
-
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer)
-{
-	u8 buf[2];
-
-	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-	/* Check if mac in i2c memory is valid */
-	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
-		/* Valid mac address is saved in i2c eeprom */
-		i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
-		return 0;
-	}
-
-	return -1;
-}
-
-static int write_mac(uchar *mac)
-{
-	u8 buf[2];
-
-	buf[0] = (u8)MAGIC_BYTE0;
-	buf[1] = (u8)MAGIC_BYTE1;
-	i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-	buf[0] = (u8)~MAGIC_BYTE0;
-	buf[1] = (u8)~MAGIC_BYTE1;
-
-	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-	/* check if valid MAC address is saved in I2C EEPROM or not? */
-	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
-		i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
-		puts("I2C EEPROM written with mac address \n");
-		return 0;
-	}
-
-	puts("I2C EEPROM writing failed\n");
-	return -1;
-}
-#endif
-
-int do_chip_config(struct cmd_tbl *cmdtp, int flag, int argc,
-		   char *const argv[])
-{
-	void (*sram_setfreq) (unsigned int, unsigned int);
-	unsigned int frequency;
-#if defined(CONFIG_CMD_NET)
-	unsigned char mac[6];
-#endif
-
-	if ((argc > 3) || (argc < 2))
-		return cmd_usage(cmdtp);
-
-	if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
-
-		frequency = simple_strtoul(argv[2], NULL, 0);
-
-		if (frequency > 333) {
-			printf("Frequency is limited to 333MHz\n");
-			return 1;
-		}
-
-		sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
-
-		if (!strcmp(argv[1], "cpufreq")) {
-			sram_setfreq(CPU, frequency);
-			printf("CPU frequency changed to %u\n", frequency);
-		} else {
-			sram_setfreq(DDR, frequency);
-			printf("DDR frequency changed to %u\n", frequency);
-		}
-
-		return 0;
-
-#if defined(CONFIG_CMD_NET)
-	} else if (!strcmp(argv[1], "ethaddr")) {
-
-		u32 reg;
-		char *e, *s = argv[2];
-		for (reg = 0; reg < 6; ++reg) {
-			mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-		write_mac(mac);
-
-		return 0;
-#endif
-	} else if (!strcmp(argv[1], "print")) {
-#if defined(CONFIG_CMD_NET)
-		if (!i2c_read_mac(mac)) {
-			printf("Ethaddr (from i2c mem) = %pM\n", mac);
-		} else {
-			printf("Ethaddr (from i2c mem) = Not set\n");
-		}
-#endif
-		return 0;
-	}
-
-	return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
-	   "configure chip",
-	   "chip_config cpufreq/ddrfreq frequency\n"
-#if defined(CONFIG_CMD_NET)
-	   "chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
-#endif
-	   "chip_config print");
diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S
deleted file mode 100644
index 9ac96291b7..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/start.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  armboot - Startup Code for ARM926EJS CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
- */
-
-
-#include <config.h>
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * The BootROM already initialized its own stack in the [0-0xb00] reserved
- * range of the SRAM. The SPL (in _main) will update the stack pointer to
- * its own SRAM area (right before the gd section).
- *
- *************************************************************************
- */
-
-	.globl	reset
-	.globl	back_to_bootrom
-
-reset:
-	/*
-	* SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
-	* UART boot, USB boot): save registers in BootROM's stack and then the
-	* BootROM's stack pointer in the SPL's data section.
-	*/
-	push	{r0-r12,lr}
-	ldr	r0, =bootrom_stash_sp
-	str	sp, [r0]
-
-	/*
-	 * Flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* Flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* Flush v4 TLB */
-
-	/*
-	 * Enable instruction cache
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
-	mcr	p15, 0, r0, c1, c0, 0
-
-	/*
-	 * Go setup Memory and board specific bits prior to relocation.
-	 * This call is not supposed to return.
-	 */
-	b	_main	/* _main will call board_init_f */
-
-back_to_bootrom:
-	pop	{r0-r12,pc}
diff --git a/arch/arm/cpu/arm926ejs/spear/timer.c b/arch/arm/cpu/arm926ejs/spear/timer.c
deleted file mode 100644
index d5f6cccaae..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ /dev/null
@@ -1,121 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- */
-
-#include <common.h>
-#include <init.h>
-#include <time.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_gpt.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/ptrace.h>
-#include <linux/delay.h>
-
-#define GPT_RESOLUTION	(CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
-#define READ_TIMER()	(readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
-
-static struct gpt_regs *const gpt_regs_p =
-    (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
-
-static struct misc_regs *const misc_regs_p =
-    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static ulong get_timer_masked(void);
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-int timer_init(void)
-{
-	u32 synth;
-
-	/* Prescaler setting */
-#if defined(CONFIG_SPEAR600)
-	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
-	synth = MISC_GPT3SYNTH;
-#else
-# error Incorrect config. Can only be SPEAR{600|300|310|320}
-#endif
-
-	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
-	       &misc_regs_p->periph_clk_cfg);
-
-	/* disable timers */
-	writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
-
-	/* load value for free running */
-	writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
-
-	/* auto reload, start timer */
-	writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
-
-	/* Reset the timer */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
-	return (get_timer_masked() / GPT_RESOLUTION) - base;
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong start = get_timer_masked();
-	ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
-	ulong rndoff;
-
-	rndoff = (usec % 10) ? 1 : 0;
-
-	/* tenudelcnt timer tick gives 10 microsecconds delay */
-	tmo = ((usec / 10) + rndoff) * tenudelcnt;
-
-	while ((ulong) (get_timer_masked() - start) < tmo)
-		;
-}
-
-static ulong get_timer_masked(void)
-{
-	ulong now = READ_TIMER();
-
-	if (now >= lastdec) {
-		/* normal mode */
-		timestamp += now - lastdec;
-	} else {
-		/* we have an overflow ... */
-		timestamp += now + GPT_FREE_RUNNING - lastdec;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SPEAR_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
deleted file mode 100644
index 0964a9742e..0000000000
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- */
-
-MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
-		LENGTH = IMAGE_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	.text      :
-	{
-		__start = .;
-		*(.vectors)
-		CPUDIR/spear/start.o	(.text*)
-		*(.text*)
-	} > .sram
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
-	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	} > .sram
-
-	. = ALIGN(4);
-	__image_copy_end = .;
-	_end = .;
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start = .;
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_end = .;
-	} > .sram
-}