diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2018-03-21 15:59:00 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2018-03-21 17:06:54 +0300 |
| commit | c75eeb0bcbd5596f2b4e2b81eaa572675f019906 (patch) | |
| tree | 578f0bc927509438758a07429c249ca08bac16d0 /arch/arc | |
| parent | 48b04832d8a2045c8e72c5a0c8e7e54043fe670d (diff) | |
ARC: Cache: Implement [i,d]cache_enabled() as separate functions
Implement icache_enabled() and dcache_enabled() as separate functions
which can be used with "inline" attribute. This is a preparation to
make them always_inline.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/lib/cache.c | 38 |
1 files changed, 21 insertions, 17 deletions
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index ad14900135..7052895bb7 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -132,6 +132,14 @@ static inline bool icache_exists(void) return !!ibcr.fields.ver; } +static inline bool icache_enabled(void) +{ + if (!icache_exists()) + return false; + + return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE); +} + static inline bool dcache_exists(void) { union bcr_di_cache dbcr; @@ -140,6 +148,14 @@ static inline bool dcache_exists(void) return !!dbcr.fields.ver; } +static inline bool dcache_enabled(void) +{ + if (!dcache_exists()) + return false; + + return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE); +} + static inline bool slc_exists(void) { if (is_isa_arcv2()) { @@ -357,13 +373,7 @@ void cache_init(void) int icache_status(void) { - if (!icache_exists()) - return 0; - - if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) - return 0; - else - return 1; + return icache_enabled(); } void icache_enable(void) @@ -383,7 +393,7 @@ void icache_disable(void) /* IC supports only invalidation */ static inline void __ic_entire_invalidate(void) { - if (!icache_status()) + if (!icache_enabled()) return; /* Any write to IC_IVIC register triggers invalidation of entire I$ */ @@ -408,13 +418,7 @@ void invalidate_icache_all(void) int dcache_status(void) { - if (!dcache_exists()) - return 0; - - if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) - return 0; - else - return 1; + return dcache_enabled(); } void dcache_enable(void) @@ -484,7 +488,7 @@ static inline void __dc_entire_op(const int cacheop) { int aux; - if (!dcache_status()) + if (!dcache_enabled()) return; __before_dc_op(cacheop); @@ -502,7 +506,7 @@ static inline void __dc_entire_op(const int cacheop) static inline void __dc_line_op(unsigned long paddr, unsigned long sz, const int cacheop) { - if (!dcache_status()) + if (!dcache_enabled()) return; __before_dc_op(cacheop); |