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authorVlad Zakharov <vzakhar@synopsys.com>2017-03-21 14:49:47 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2017-03-24 14:20:55 +0300
commitad9b5f77dffaa38ea830af94cd5de3450318f97c (patch)
tree3bb41583e0f1dada28c659aafabd7cc240c88cba /arch/arc
parentd0ffda8ed208ff2957cd09ccc37e2d6dff81523e (diff)
drivers: timer: Introduce ARC timer driver
This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/include/asm/arcregs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index cf999b0280..54a9b00d4c 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -33,6 +33,10 @@
#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
+#define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
+#define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
+#define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */
+
#define ARC_AUX_INTR_VEC_BASE 0x25
/* Data cache related auxiliary registers */