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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2018-03-26 15:57:38 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2018-04-02 12:27:56 +0300
commitf770b3ee1830a5fbd3b44cd051d9e5468339d651 (patch)
treef229ce78100ee5d5268613ffdc412209d62e32f1 /arch/arc
parentada8affdfe32bb621db09332a8267bab4ae5f312 (diff)
ARC: HSDK: Enable SPI flash support
HSDK board has sst26wf016 SPI flash IC which we want to support. Add SPI controller, CS-gpio and SPI flash nodes to hsdk device tree. Enable corresponding options in hsdk defconfig. For SPI write functionality to work we need [1] which adds support of sst26xxx ICs. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=35796 Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/dts/hsdk.dts26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 09f3fe9a37..80b864af74 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -14,6 +14,7 @@
aliases {
console = &uart0;
+ spi0 = &spi0;
};
cpu_card {
@@ -83,4 +84,29 @@
compatible = "generic-ohci";
reg = <0xf0060000 0x100>;
};
+
+ spi0: spi@f0020000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xf0020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <4000000>;
+ clocks = <&cgu_clk CLK_SYS_SPI_REF>;
+ clock-names = "spi_clk";
+ cs-gpio = <&cs_gpio 0>;
+ spi_flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+ };
+
+ cs_gpio: gpio@f00014b0 {
+ compatible = "snps,hsdk-creg-gpio";
+ reg = <0xf00014b0 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "hsdk-spi-cs";
+ gpio-count = <1>;
+ };
};