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authorAlexey Brodkin <Alexey.Brodkin@synopsys.com>2015-05-18 16:56:26 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2015-07-01 17:17:27 +0300
commitef639e6f7076c19959f40f367cead5108d099592 (patch)
treecea7b5dba213bd2a88041cca9485e19a75d0e3df /arch/arc/lib/cpu.c
parent8b2eb776b13055e71f94367c06a26c5e3a902f16 (diff)
arc: significant cache rework
[1] Align cache management functions to those in Linux kernel. I.e.: a) Use the same functions for all cache ops (D$ Inv/Flush) b) Split cache ops in 3 sub-functions: "before", "lineloop" and "after". That way we may re-use "before" and "after" functions for region and full cache ops. [2] Implement full-functional L2 (SLC) management. Before SLC was simply disabled early on boot. It's also possible to enable or disable L2 cache from config utility. [3] Disable/enable corresponding caches early on boot. So if U-Boot is configured to use caches they will be used at all times (this is useful in partucular for speed-up of relocation). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc/lib/cpu.c')
-rw-r--r--arch/arc/lib/cpu.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c
index 3c930bcbeb..4e4dd74db3 100644
--- a/arch/arc/lib/cpu.c
+++ b/arch/arc/lib/cpu.c
@@ -23,6 +23,8 @@ int arch_cpu_init(void)
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ cache_init();
+
return 0;
}