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authorAlex Waterman <awaterman@dawning.com>2011-05-19 15:08:36 -0400
committerScott Wood <scottwood@freescale.com>2011-07-01 15:56:52 -0500
commiteced4626e4d8ea2fd2662045dc7aad0f07db7a41 (patch)
treeb69ea937b15426b9a4c19521ee5f8420531cee84 /README
parentc9494866df835bcee68e17339aec1090faa704da (diff)
NAND: Add 16bit NAND support for the NDFC
This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added: CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a 16 bit device is attached. CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus Controller configuration register. Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian. The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used. Signed-off-by: Alex Waterman <awaterman@dawning.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'README')
-rw-r--r--README8
1 files changed, 8 insertions, 0 deletions
diff --git a/README b/README
index 446966dc16f..a760cf35675 100644
--- a/README
+++ b/README
@@ -2917,6 +2917,14 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_SRIOn_MEM_SIZE:
Size of SRIO port 'n' memory region
+- CONFIG_SYS_NDFC_16
+ Defined to tell the NDFC that the NAND chip is using a
+ 16 bit bus.
+
+- CONFIG_SYS_NDFC_EBC0_CFG
+ Sets the EBC0_CFG register for the NDFC. If not defined
+ a default value will be used.
+
- CONFIG_SPD_EEPROM
Get DDR timing information from an I2C EEPROM. Common
with pluggable memory modules such as SODIMMs