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authorAshish Kumar <Ashish.Kumar@nxp.com>2017-08-11 11:09:14 +0530
committerYork Sun <york.sun@nxp.com>2017-09-11 07:55:36 -0700
commit63b2316c5c4ba0e47d1f69ef1372db4fd89b6bf5 (patch)
tree065b8277ffa5951efbff0a53bdb8a6f797d7b884 /README
parent584f316f115df52fd09a6cf699b29dcf824b4da5 (diff)
fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
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diff --git a/README b/README
index a46850c8085..c0c8b559f9b 100644
--- a/README
+++ b/README
@@ -312,6 +312,15 @@ Many of the options are named exactly as the corresponding Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
+- ARM Platform Bus Type(CCI):
+ CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+ provides full cache coherency between two clusters of multi-core
+ CPUs and I/O coherency for devices and I/O masters
+
+ CONFIG_SYS_FSL_HAS_CCI400
+
+ Defined For SoC that has cache coherent interconnect
+ CCN-400
The following options need to be configured: